Low Power Adder Circuit Based on Coupling Technique
Today’s technology is continuously scaling itself, thereby resulting in increasing density of the transistors leading to high power dissipation on the chip. Therefore, we need to reduce this power consumption of these circuits and make them more efficient. In this paper, we have introduced two transistors in the Static Energy Recovery Full adder circuit by twisted coupled technique to achieve the power reduction of the circuit. The circuitry proposed in this paper is intended to be operated at 1 V supply with 0.12 mW on 90 nm CMOS technology.
KeywordsAdders MOS SERF Low power
- 1.Murmann, B. et al. “Impact of scaling on analog performance and associated modeling needs” IEEE Trans. Electronic Devices vol. 53 no. 9 pp. 2160–2167 Sep. 2006.Google Scholar
- 2.Uyemura, J. P. “Introduction to VLSI Circuits and Systems” Wiley John & Sons Inc. 2002.Google Scholar
- 3.Kumar, M., Arya, S. K. and Pandey, S., “Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate,” International Journal of VLSI design & Communication Systems, vol. 2, no. 4, pp. 47–59, December 2011.Google Scholar
- 4.Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, “A Novel High Speed And Energy Efficient 10 Transistor Full Adder Design,” IEEE Transactions On Circuits And Systems—I: Regular Papers, vol. 54, no. 5, pp. 1053–54, May 2007.Google Scholar
- 5.Alluri, S., Dasharatha, M., Naik, B. R., “Design of low power high speed full adder cell with XOR/XNOR logic gates”, 2016 International Conference on Communication and Signal Processing (ICCSP), pp. 0565–0570, DOI: 10.1109/ICCSP.2016.7754203.
- 6.Singhal, S., Gaur, N., Mehra, A., Kumar, P., “Analysis and Comparison of Leakage Power Reduction Techniques In CMOS Citcuits,” IEEE Conference on SPIN, Feb. 2015, pp. 936–944, DOI: 10.1109/SPIN.2015.7095351.
- 7.Ahn, S. Y. and Cho, K., “Small-Swing Domino Logic Based on Twist-Connected Transistors,” Elec. Letters, vol. 50, no. 15, pp. 1054–1056, July 2014.Google Scholar
- 8.Mehra, A., Bahukhandi, A., Kaur, A., Katyar, S., Khajuria, S., Rajput, S. K., Gaur, N., “A Novel Power Efficient 12T Full Adder”, International Journal of Simulation Systems, Science & Technology, vol. 15, pp 44–48, 2014.Google Scholar