Constrained Level Validation of Serial Peripheral Interface Protocol
The motivation behind this paper is to give a full portrayal of a state-of-the-art SPI master/slave usage. Every single related issue, beginning from the elaboration of introductory details, till the last framework confirmation, is thoroughly examined and justified. In similarity with outline reuse approach, the concerned paper imparts high-grade intellectual properties i.e., IP’s that concerns in gathering all essential components that help in achieving presently required and modern ASIC or SoC applications using this SPI master and slave protocol. SPI is a standout among the most usually utilized serial interface protocols.
KeywordsSystem on chip (SoC) Serial to peripheral interface (SPI) Control registers Verilog Constraints ARM
The authors would like to thank the entire semiconductor team at CYIENT and the staff of KL University for their immense support and motivation in implementing this paper. Without their guidance, this paper would not have seen the light of the day.
- 1.Pachler, W., Pressel, K., Grosinger, J., Beer, G., Bosch, W., Holweg, G., Zilch, C., Meindl, M.: A novel 3D packaging concept for RF powered sensor grains. In: 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), pp. 1183–1188 (2014)Google Scholar
- 2.Das, R., Singh, G.K., Mehra, R.M.: Two-phase clocking scheme for low-power and high-speed VLSI. Int. J. Adv. Eng. Sci. Technol. 2(2), 225–230 (2013)Google Scholar
- 3.Bais, A., Singh, G.K., Mehra, R.M.: Design of 6-T SRAM cell for enhanced read/write margin. Int. J. Adv. Electr. Electron. Eng. 2(2), 317–325 (2013)Google Scholar
- 4.Aditya, K., Sivakumar, M., Noorbasha, F., Praveen Blessington, T.: Design and functional verification of a SPI master slave core using system verilog. In: IJSCE, vol. 2(2), ISSN:2231-2307 (2012)Google Scholar
- 5.Liu, T., Wang, Y.: IP Design of Universal Multiple Devices SPI Interface. Department of Electronic Engineering, Xiamen University, IEEE (2011)Google Scholar
- 6.Sandya, M., Rajasekhar, K.: Design and verification of serial peripheral interface. Int. J. Eng. Trends Technol. 3(4), 522–524 (2012)Google Scholar
- 7.SPI Block Guide V03.06, Document number S12SPIV3/D, Original Release Date: 21 JAN (2000), Revised: 04 FEB (2003), MOTOROLA INCGoogle Scholar
- 8.Oudjida, A.K., Berrandjia, M.L., Liacha, A., Tiar, R., Tahraoui, K., Alhoumays, Y.N.: Design and test of general purpose SPI Master/Slave IPs on OPB bus.In: 2010 7th International Multi-conference on Systems Signals and Devices (SSD), 27–30 June. IEEE Press, Amman (2010)Google Scholar
- 9.Oudjida, K., Berrandjia, M.L., Tiar, R., Liacha, A., Tahraoui, K.: FPGA implementation of I2C and SPI protocols: a comparative study. In: Proceedings 16th IEEE International Conference on Electronics, Circuits, and Systems, pp. 507–510 (2009)Google Scholar