Advertisement

A Radiation Hardening Algorithm on 2nd Order CDR

  • Hu ChunmeiEmail author
  • Chen Shuming
  • Liu Yao
  • Chen Jianjun
  • Xu Jingyan
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 666)

Abstract

A radiation hardening algorithm named as state-conservation on 2nd order clock and data recovery (CDR) system is presented in this paper. This proposed algorithm is used to resist the single event transient (SET) of CDR tracking loop. A MATLAB model is established to fast evaluate the sensitive position of the system. A circuit model of 5 Gbps half rate CDR together with the hardening algorithm is set up to verify the effect of the proposed algorithm in Cadence design environment. The simulation result shows that SET does not lead to any error data and no loop delay is added. Compared to the RHBD standard-cell technique, the hardening algorithm saves area about 15.3% and reduces power consumption about 47.8%.

Keywords

Clock and data recovery Pulse injection State-conservation algorithm Accumulator 

Notes

Acknowledgments

This work was supported by Nature Science Foundation of China (Grant No: 61434007, 61376109, 61504169).

References

  1. 1.
    He, M.Y., Poulton, J.: A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. IEEE J. Solid-State Circ. 41(3), 597–606 (2006)CrossRefGoogle Scholar
  2. 2.
    Kromer, C., Sialm, G., Menolfi, C., Schmatz, M.: A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects. In: IEEE International Solid-state Circuits Conference, vol. 41, pp. 1266–1275 (2006)Google Scholar
  3. 3.
    Savoj, J., Hsieh, K., Upadhyaya, P., An, F.T., Im, J., Jiang, X., et al.: Design of high-speed wireline transceivers for backplane communications in 28 nm CMOS. In: Proceedings of the Custom Integrated Circuits Conference, pp. 1–4 (2012)Google Scholar
  4. 4.
    Zhang, Y., Gai, W.: SSC tracking analysis and a deeper-SSC estimator. In: IEEE International Symposium on Circuits & Systems, pp. 1408–1411 (2013)Google Scholar
  5. 5.
    Chang, H.H., Yang, R.J., Liu, S.I.: Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans. Circ. Syst. I 51(12), 2356–2364 (2004)CrossRefGoogle Scholar
  6. 6.
    Premkishore, S., Michael, K., Stephen, W.K., Burger, D., Lorenzo, A.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings International Conference on Dependable Systems and Networks, DSN 2002, pp. 389–398 (2010)Google Scholar
  7. 7.
    Mahatme, N.N., Jagannathan, S., Loveless, T.D., Massengill, L.W., Bhuva, B.L., Wen, S.J., et al.: Comparison of combinational and sequential error rates for a deep submicron process. IEEE Trans. Nucl. Sci. 58(6), 2719–2725 (2011)CrossRefGoogle Scholar
  8. 8.
    datasheet of HXSRD01 Trivor. www.honeywell.com
  9. 9.
    Armstrong, S.E., Olson, B.D., Holman, W.T., Warner, J., Mcmorrow, D., Massengill, L.W.: Demonstration of a differential layout solution for improved ASET tolerance in CMOS A/MS circuits. IEEE Trans. Nucl. Sci. 57, 3615–3619 (2010)Google Scholar
  10. 10.
    Hu, C., Chen, S., Huang, P., Liu, Y., Chen, J.: Evaluating the single event sensitivity of dynamic comparator in 5Gbps SerDes. IEICE Electron. Express 12(23), 1–6 (2015)Google Scholar
  11. 11.
    Liu, Y., Yum, T.Y., Xue, Q., Chan, C.H.: A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. IEEE J. Solid-State Circ. 39(4), 613–621 (2004)CrossRefGoogle Scholar
  12. 12.
    Chen, W.C., Tsai, C.C., Chang, C.H., Peng, Y.C.: A 2.5-8 Gb/s transceiver with 5-tap DFE and second order CDR against 28-inch channel and 5000 ppm SSC in 40 nm CMOS technology. In: IEEE Custom Integrated Circuits Conference, pp. 1–4 (2010)Google Scholar
  13. 13.
    Wang, S., Mei, H., Baig, M., Bereza, W.: Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. In: Custom Integrated Circuits Conference, pp. 317–320 (2005)Google Scholar
  14. 14.
    Du, Y., Chen, S., Liu, B.: Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells. Microelectron. J. 44(2), 65–71 (2013)CrossRefGoogle Scholar
  15. 15.
    Bin, L., Yankang, D., Hui, X.: Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology. IEICE Electron. Express 11(19), 1–6 (2014)CrossRefGoogle Scholar
  16. 16.
    Bing, L., Ruiqiang, S.: Analyzing and mitigation the internal single-event transient in radiation hardened flip-flop at circuit-level. Sci. China Tech. Sci. 57, 1834–1839 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2016

Authors and Affiliations

  • Hu Chunmei
    • 1
    Email author
  • Chen Shuming
    • 1
    • 2
  • Liu Yao
    • 1
  • Chen Jianjun
    • 1
  • Xu Jingyan
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaPeople’s Republic of China
  2. 2.National Laboratory for Parallel and Distributed ProcessingNational University of Defense TechnologyChangshaPeople’s Republic of China

Personalised recommendations