An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits

  • Philip C. Jose
  • S. Karthikeyan
  • K. Batri
  • S. Sivanantham
Conference paper
First Online:
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 452)

Abstract

Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.

Keywords

Gate replacement algorithm Leakage current Subthreshold leakage Gate oxide leakage SAT solver 
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Copyright information

© Springer Science+Business Media Singapore 2016

Authors and Affiliations

  • Philip C. Jose
    • 1
  • S. Karthikeyan
    • 2
  • K. Batri
    • 2
  • S. Sivanantham
    • 1
  1. 1.School of Electronics EngineeringVIT UniversityVelloreIndia
  2. 2.Department of Electronics and Communication EngineeringPSNA College of Engineering and TechnologyDindigulIndia

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