Advanced Architectures for 3D NAND Flash Memories with Vertical Channel

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Abstract

One of the key metrics to benchmark different 3D architectures is the storage density, which is here indicated with Bit_Density. Given a specific Flash memory die, this density is defined as the ratio between the storage capacity of the die, Die_Capacity, and its silicon area, Die_Size. In this chapter we present some of the most advanced architectures of 3D arrays with vertical channels, which were mainly developed to increase Bit_Density and reduce the Source Line effect.

Keywords

Line Contact Charge Pump Vertical Channel Control Gate Silicon Area 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer Science+Business Media Dordrecht 2016

Authors and Affiliations

  1. 1.Performance Storage BUMicrosemi CorporationVimercateItaly

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