Circuit Fault Detection Using Industrial Cadence Software

  • C. Baron
  • P. Bourdeu D’Aguerre
  • F. Caignet
  • A. Ferreira
  • J.-C. Geffroy
Conference paper

Abstract

With technology improvement and growing complexity of micro-electronic circuits, the verification of the system functionality has become one of the major current problems [2]. In the educational context of the engineering Training Pole in Microelectronics located in Toulouse, France (PFMT), several lectures and their associated labs on electronic systems reliability have been recently established. The PFMT regroups students in their last year of studies from five engineering schools and universities. This paper presents (section 2) the main outlines of the lecture concerning on-line/off-line testing methodologies [3], [4], which are nowadays an industrial requirement. Examples of application are also described in section 3.

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References

  1. [1]
  2. [2]
    B. COURTOIS « CAD and Testing of Ics and Systems, Where are we going ? » reprinted from Journal of Microelectronic systems Integration, Vol. 2, No. 3 1994.Google Scholar
  3. [3]
    « VLSI testing » au]T.W. Williams editor, Advances in CAD for VLSI, Vol. No. 5, North-Holland, 1986.Google Scholar
  4. [4]
    A. Miczo, « Digital Logic Testing and Simulation » Harper & Row Pub., New York, 1986.Google Scholar
  5. [5]
    C. BARON « Identification of Sequential Systems », PhD report, INSA Toulouse, nov. 1995.Google Scholar
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Copyright information

© Springer Science+Business Media Dordrecht 1998

Authors and Affiliations

  • C. Baron
    • 1
  • P. Bourdeu D’Aguerre
    • 1
  • F. Caignet
    • 1
  • A. Ferreira
    • 1
  • J.-C. Geffroy
    • 1
  1. 1.Complexe Scientifique de RangueilLESIA, INSA ToulouseToulouse CedexFrance

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