Efficient Wear Leveling in NAND Flash Memory

Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 37)

Abstract

In the recent years, flash storage devices such as solid-state drives (SSDs) and flash cards have become a popular choice for the replacement of hard disk drives, especially in the applications of mobile computing devices and consumer electronics. However, the physical constraints of flash memory pose a lifetime limitation on these storage devices. New technologies for ultra-high density flash memory such as multilevel-cell (MLC) flash further degrade flash endurance and worsen this lifetime concern. As a result, flash storage devices may experience a unexpectedly short lifespan, especially when accessing these devices with high frequencies. In order to enhance the endurance of flash storage device, various wear leveling algorithms are proposed to evenly erase blocks of the flash memory so as to prevent wearing out any block excessively. In this chapter, various existing wear leveling algorithms are investigated to point out their design issues and potential problems. Based on this investigation, two efficient wear leveling algorithms (i.e., the evenness-aware algorithm and dual-pool algorithm) are presented to solve the problems of the existing algorithms with the considerations of the limited computing power and memory space in flash storage devices. The evenness-aware algorithm maintains a bit array to keep track of the distribution of block erases to prevent any cold data from staying in any block for a long period of time. The dual-pool algorithm maintains one hot pool and one cold pool to maintain the blocks that store hot data and cold data, respectively, and the excessively erased blocks in the hot pool are exchanged with the rarely erased blocks in the cold pool to prevent any block from being erased excessively. In this chapter, a series of explanations and analyses shows that these two wear leveling algorithms could evenly distribute block erases to the whole flash memory to enhance the endurance of flash memory.

Keywords

Flash Memory Garbage Collection Logical Block Cold Pool Garbage Collector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    A. Ban, Flash file system, US Patent 5,404,485, in M-Systems, Apr 1995Google Scholar
  2. 2.
    A. Ban, Wear leveling of static areas in flash memory, US Patent 6732221 (2004)Google Scholar
  3. 3.
    A. Ban, R. Hasbaron, Wear leveling of static areas in flash memory, US Patent 6,732,221, in M-systems, May 2004Google Scholar
  4. 4.
    A. Ben-Aroya, S. Toledo, Competitive analysis of flash-memory algorithms, in Proceedings of the 14th Conference on Annual European Symposium (2006)Google Scholar
  5. 5.
    L.-P. Chang, On efficient wear-leveling for large-scale flash-memory storage systems, in 22nd ACM Symposium on Applied Computing (ACM SAC), Mar 2007Google Scholar
  6. 6.
    L.-P. Chang, T.-W. Kuo, Efficient management for large-scale flash-memory stroage systems with resource conservation. ACM Trans. Storage 1(4), 381–418 (2005)CrossRefGoogle Scholar
  7. 7.
    L.-P. Chang, T.-W. Kuo, S.-W. Lo, Real-time garbage collection for flash-memory storage systems of real-time embedded systems. ACM Trans. Embed. Comput. Syst. 3(4), 837–863 (2004)CrossRefGoogle Scholar
  8. 8.
    Y.-H. Chang, J.-W. Hsieh, T.-W. Kuo, Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design, in DAC’07: Proceedings of the 44th Annual Conference on Design Automation, New York, NY, USA (ACM, 2007), pp. 212–217Google Scholar
  9. 9.
    M.-L. Chiang, P.C.H. Lee, R. chuan Chang, Using data clustering to improve cleaning performance for flash memory. Softw. Pract. Exp. 29(3), 267–290 (1999)Google Scholar
  10. 10.
    R.J. Defouw, T. Nguyen, Method and system for improving usable life of memory devices using vector processing, US Patent 7139863 (2006)Google Scholar
  11. 11.
    DRAM market-share games shifting from a knockout to a marathon; 4xnm process and multi-bit/cell as fundamental criteria to judge NAND Flash production competitiveness. Technical report, DRAMeXchange, Apr 2008Google Scholar
  12. 12.
    R.A.R.P. Estakhri, M. Assar, B. Iman, Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory. US Patent 5835935 (1998)Google Scholar
  13. 13.
    Flash Cache Memory Puts Robson in the Middle. IntelGoogle Scholar
  14. 14.
    Flash-memory Translation Layer for NAND flash (NFTL). M-Systems (1998)Google Scholar
  15. 15.
    Freescale Semiconductor. USB Thumb Drive reference design DRM061 (2004)Google Scholar
  16. 16.
    FTL Logger Exchanging Data with FTL Systems. Technical report, IntelGoogle Scholar
  17. 17.
    C.J. Gonzalez, K.M. Conley, Automated wear leveling in non-volatile storage systems, US Patent 7120729 (2006)Google Scholar
  18. 18.
    Increasing Flash Solid State Disk Reliability. Technical report, SiliconSystems, Apr 2005Google Scholar
  19. 19.
    J.-U. Kang, H. Jo, J.-S. Kim, J. Lee, A superblock-based flash translation layer for NAND flash memory, in EMSOFT ’06: Proceedings of the 6th ACM and IEEE International Conference on Embedded Software, New York, NY, USA (ACM, 2006), pp. 161–170Google Scholar
  20. 20.
    Ken Perdue. Wear Leveling (2008)Google Scholar
  21. 21.
    H.-J. Kim, S.-G. Lee, An effective flash memory manager for reliable flash memory space management. IEICE Trans. Inf. Syst. 85(6), 950–964 (2002)Google Scholar
  22. 22.
    J. Kim, J.-M. Kim, S. Noh, S.-L. Min, Y. Cho, A Space-Efficient Flash Translation Layer for Compactflash Systems. IEEE Trans. Consum. Electron. 48(2), 366–375 (2002)CrossRefGoogle Scholar
  23. 23.
    S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, H.-J. Song, A log buffer-based flash translation layer using fully-associative sector translation. Trans. Embed. Comput. Syst. 6(3), 18 (2007)Google Scholar
  24. 24.
    Micron Technology. Wear-Leveling Techniques in NAND Flash Devices (2008)Google Scholar
  25. 25.
    Microsoft, Flash-memory abstraction layer (FAL), in Windows Embedded CE 6.0 Source Code (2007)Google Scholar
  26. 26.
    Motorola, Inc., MC9S12UF32 System on a Chip Guide V01.04 (2002)Google Scholar
  27. 27.
    M-Systems. Flash-Memory Translation Layer for NAND Flash (NFTL) (1998)Google Scholar
  28. 28.
    M-Systems. TrufFFS Wear-Leveling Mechanism, Technical Note TN-DOC-017 (2002)Google Scholar
  29. 29.
    NAND08Gx3C2A 8Gbit Multi-level NAND Flash Memory. STMicroelectronics (2005)Google Scholar
  30. 30.
    Numonyx, Wear Leveling in NAND Flash Memories (2008)Google Scholar
  31. 31.
    Open NAND Flash Interface (ONFi), Open NAND Flash Interface Specification Revision 2.1 (2009)Google Scholar
  32. 32.
    C. Ruemmler, J. Wilkes, UNIX disk access patterns, in Usenix Conference (Winter 1993), pp. 405–420Google Scholar
  33. 33.
    D. Roselli, J.R. Lorch, T.E. Anderson, A comparison of file system workloads, in Proceedings of the USENIX Annual Technical Conference, pp. 41–54Google Scholar
  34. 34.
    M. Rosenblum, J.K. Ousterhout, The design and implementation of a log-structured file system. ACM Trans. Comput. Syst. 10(1) (1992)Google Scholar
  35. 35.
    Samsung Electronics, K9F2808U0B 16M * 8 Bit NAND Flash Memory Data Sheet (2001)Google Scholar
  36. 36.
    Samsung Electronics Company, K9GAG08U0M 2G * 8 Bit MLC NAND Flash Memory Data Sheet (Preliminary)Google Scholar
  37. 37.
    Samsung Electronics Company, K9NBG08U5M 4Gb * 8 Bit NAND Flash Memory Data SheetGoogle Scholar
  38. 38.
    SanDisk Corporation, Sandisk Flash Memory Cards Wear Leveling (2003)Google Scholar
  39. 39.
    D. Shmidt, Technical note: Trueffs wear-leveling mechanism (tn-doc-017). Technical report, M-System (2002)Google Scholar
  40. 40.
    Software Concerns of Implementing a Resident Flash Disk. IntelGoogle Scholar
  41. 41.
    Spectek, NAND Flash Memory MLC (2003)Google Scholar
  42. 42.
    M. Spivak, S. Toledo, Storing a persistent transactional object heap on flash memory, in LCTES ’06: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Language, Compilers, and Tool Support for Embedded Systems (2006), pp. 22–33Google Scholar
  43. 43.
    STMicroelectronics, Wear Leveling in Single Level Cell NAND Flash Memories (2006)Google Scholar
  44. 44.
    S. P. D.-H. L. S.-W. L. Tae-Sun Chung, Dong-Joo Park, H.-J. Song, System software for flash memory: a survey, in EUC ’06: Embedded and Ubiquitous Computing (2006), pp. 394–404Google Scholar
  45. 45.
    Understanding the Flash Translation Layer (FTL) Specification. Technical report, Intel Corporation (Dec 1998), http://developer.intel.com/
  46. 46.
    W. Vogels, File system usage in windows nt 4.0. SIGOPS Oper. Syst. Rev. 33(5), 93–109 (1999)Google Scholar
  47. 47.
    D. Woodhouse, Jffs: the journalling flash file system, in Proceedings of Ottawa Linux Symposium (2001)Google Scholar
  48. 48.
    M. Wu, W. Zwaenepoel, eNVy: a non-volatile main memory storage system, in Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (1994), pp. 86–97Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.Academia SinicaInstitute of Information ScienceTaipeiTaiwan
  2. 2.Department of Computer ScienceNational Chiao-Tung UniversityHsinchuTaiwan

Personalised recommendations