Protecting Circuits Against Hold Time Violations
Due to Process Variability
In this chapter, we show how to protect digital circuits against hold time violations due to process variability. First, a motivation in this issue is drawn. Then different options of how to provide the protection are presented.
KeywordsShort Path Setup Time Critical Path Digital Circuit Race Condition
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- 6.BLAAUW, D.; CHOPRA, K. CAD Tools for Variation Tolerance. In: Design Automation Conference, DAC, 42., 2005. Proceedings… New York: IEEE/ACM, 2005.Google Scholar
- 41.SHENOY, N. V.; BRAYTON, R. K.; SANGIOVANNI-VINCENTELLI, A. L. Minimum Padding to Satisfy Short Path Constraints. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD. Proceedings… [S.l.: s.n.], 1993. p. 156–161.Google Scholar
- 49.Visweswariah, C. Statistical Analysis and Design of Digital Integrated Circuits. Invited Presentation at EDA Forum, 2005, Hannover, Germany.Google Scholar
- 50.Visweswariah, C. Statistical Analysis and Optimization in the Presence of Gate and Interconnect Delay Variations. In: International Workshop on System Level Interconnect Prediction, SLIP, 2006, Munich. Proceedings… New York: ACM, 2006. p. 37.Google Scholar
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