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Low-Power Pipelined A/D Conversion

  • Boris MurmannEmail author
Chapter

Abstract

This paper reviews recent developments and low-power design techniques for high-speed pipelined A/D converters. The discussion spans a review of the fundamental operation principles, a summary of widely used low-power techniques, and an examination of ideas that have been proposed in recent research publications. As we will show, the best research-level designs reach a power efficiency that lies within an order of magnitude of practically achievable limits in today’s architectures. This corresponds to a 2–3 order of magnitude improvement relative to the first pipelined ADCs designed in the late 1980s and early 1990s.

Keywords

Power Dissipation Quantization Error Power Efficiency Power Saving Pipeline ADCs 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2012

Authors and Affiliations

  1. 1.Stanford UniversityStanfordUSA

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