Data Conversion Pulse-Width Modulators for Switch-Mode Power Converter Digital Control

  • Eduard Alarcón
  • Vahid Yousefzadeh
  • Aleksandar Prodić
  • Dragan Maksimović
Chapter
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Abstract

This chapter presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. In order to optimize circuit resources in terms of occupied area and power consumption, architectures based on tapped delay lines are studied, which includes segmentation of the input digital code to drive binary-weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described.

Keywords

Time Slot Delay Line Switching Frequency Digital Code Delay Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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References

  1. 1.
    B.J. Patella, A. Prodic, A. Zirger, D. Maksimovic, High-frequency digital PWM controller IC for DC-DC converters. IEEE Trans. Power Electron. 18(1), 438–446 (2003)CrossRefGoogle Scholar
  2. 2.
    V. Peterchev, J. Xiao, S.R. Sanders, Architecture and IC implementation of a digital VRM controller. IEEE Trans. Power Electron. 18(1), 356–364 (2003)CrossRefGoogle Scholar
  3. 3.
    P. Dancy, R. Amirtharajah, A.P. Chandrakasan, High-efficiency multiple-output DC–DC conversion for low-voltage systems. IEEE Trans. VLSI Syst. 8(3), 252–263 (2000)CrossRefGoogle Scholar
  4. 4.
    A.V. Peterchev, S.R. Sanders, Quantization resolution and limit cycling in digitally controlled PWM converters. IEEE Trans. Power Electron. Part 2 18(1), 301–308 (2003)CrossRefGoogle Scholar
  5. 5.
    A. Syed, E. Ahmed, E. Alarcón, D. Maksimovic, Digital PWM architectures. IEEE PESC 6, 4689–4695 (2004)Google Scholar
  6. 6.
    M. Barai, S. Sengupta, J. Biswas, Digital controller for DVS-enabled DC–DC converter. IEEE Trans. Power Electron. 25(3), 557–573 (2010)CrossRefGoogle Scholar
  7. 7.
    H. Ahmad, B. Bakkaloglu, A digitally controlled DC-DC buck converter using frequency domain ADCs, in IEEE APEC 2010, Palm Springs, 2010, pp. 1871–1874Google Scholar
  8. 8.
    E.G. Soenen, A. Roth, J. Shi, M. Kinyua, J. Gaither, E. Ortynska, A robust digital DC-DC converter with rail-to-rail output range in 40 nm CMOS, in IEEE ISSCC, 2010, Austin, 2010, pp. 198–200Google Scholar
  9. 9.
    H. Peng, A. Prodic, E. Alarcon, D. Maksimovic, Modeling of quantization effects in digitally controlled DC–DC converters. IEEE Trans. Power Electron. 22(1), 208–215 (2007)CrossRefGoogle Scholar
  10. 10.
    G.Y. Wei, M. Horowitz, A low power switching power supply for self-clocked systems, in International Symposium on Low Power Electronics and Design, 1996, Monterey, 1996, pp. 313–317Google Scholar
  11. 11.
    P. Dancy, A.P. Chandrakasan, Ultra low power control circuits for PWM converters, in IEEE PESC’97, St. Louis, 1997, pp. 21–27Google Scholar
  12. 12.
    J. Goodman, A.P. Dancy, A.P. Chandrakasan, An energy/security scalable encryption processor using an embedded variable voltage dc/dc converter. IEEE J. Solid-State Circuits 33(11), 1799 (1998)CrossRefGoogle Scholar
  13. 13.
    H. McDermott, A programmable sound processor for advanced hearing aid research. IEEE Trans. Rehabil. Eng. 6(1), 53 (1998)MathSciNetCrossRefGoogle Scholar
  14. 14.
    H. Gwee, J.S. Chang, H. Li, A micro-power low-distortion digital pulse width modulator for a digital class D amplifier. IEEE Trans. Circuits Syst. – II 49(4), 245 (2002)CrossRefGoogle Scholar
  15. 15.
    E. O’Malley, K. Rinne, A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz, in IEEE APEC 2004, Anaheim, 2004, pp. 53–59Google Scholar
  16. 16.
    A. Djemouai, M. Sawan, M. Slamani, New CMOS integrated pulse width modulator for voltage conversion application, in Proceedings of the 7th IEEE ICECS, 2000, Jounieh, 2000, pp. 116–119Google Scholar
  17. 17.
    A. Syed, Digital pulse width modulators: architectures and feed-forward compensation, M.S. thesis, Department of Electrical and Computer Engineering, University of Colorado at Boulder, May 2004Google Scholar
  18. 18.
    A. Syed, E. Ahmed, D. Maksimovic, Digital PWM controller with feed-forward compensation, in IEEE Applied Power Electronics Conference, 2004, Anaheim, 2004Google Scholar
  19. 19.
    F. Rad, W. Dally, H.T. Ng, A. Senthinathan, M.J.E. Lee, R. Rathi, J. Poulton, A low-power multiplying DLL for low-jitter multi gigahertz clock generation in highly integrated digital chips. IEEE J. Solid-State Circuits 37(12), 1414–1420 (2002)Google Scholar
  20. 20.
    J. Deveugele, M. Steyaert, A 10-bit 250-MS/s binary-weighted current-steering DAC. IEEE J. Solid-State Circuits 41(2), 320–329 (2006)CrossRefGoogle Scholar
  21. 21.
    J.M. Goldberg, M.B. Sandler, New high accuracy pulse width modulation based digital-to-analogue convertor/power amplifier. IEEE Proc. Circuits Devices Syst 141(4), 315–324 (1994)CrossRefGoogle Scholar
  22. 22.
    M. Norris, L. Marco, E. Alarcon, D. Maksimovic, Quantization noise shaping in digital PWM converters, in Power Electronics Specialists Conference, 2008. PESC 2008, Rodes, IEEE, 15–19 June 2008, pp. 127–133Google Scholar
  23. 23.
    E. O’Malley, K. Rinne, A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz. IEEE APEC 1, 53–59 (2004)Google Scholar
  24. 24.
    A. Djemouai, M. Sawan, M. Slamani, New CMOS integrated pulse width modulator for voltage conversion applications. IEEE Conf. Electron. Circuits Syst. ICECS 1, 116–119 (2000)Google Scholar
  25. 25.
    A. Parayandeh, A. Prodic, Programmable analog-to-digital converter for low-power DC–DC SMPS. IEEE Trans. Power Electron. 23(1), 500–505 (2008)CrossRefGoogle Scholar
  26. 26.
    K.M. Smith, K.M. Smedley, M. Yunhong Ma, Realization of a digital PWM power amplifier using noise and ripple shaping, in Proceedings IEEE PESC Conference, 1995, Atlanta, 1995, pp. 96–102Google Scholar
  27. 27.
    Z. Lu, Z. Qian, Y. Zeng, W. Yao, G. Chen, Y. Wang, Reduction of digital PWM limit ring with novel control algorithm, in Proceedings of IEEE APEC Conference, 2001, Anaheim, 2001, pp. 521–525Google Scholar
  28. 28.
    Z. Lukic, K. Wang, A. Prodic, High-frequency digital controller for dc–dc converters based on multi-bit sigma–delta pulse-width modulation, in Proceedings of IEEE APEC Conference, 2005, Austin, 2005, pp. 35–40Google Scholar
  29. 29.
    A. Kelly, K. Rinne, High resolution DPWM in a dc–dc converter application using digital sigma–delta techniques, in Proceedings of IEEE PESC Conference, 2005, Recife, 2005, pp. 1458–1463Google Scholar
  30. 30.
    Z. Lukić, N. Rahman, A. Prodić, Multibit ΣΔ PWM digital controller IC for DC-DC converters operating at switching frequencies beyond 10 MHz. IEEE Trans. Power Electron. 22(5), 1693–1707 (2007)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2012

Authors and Affiliations

  • Eduard Alarcón
    • 1
  • Vahid Yousefzadeh
    • 2
  • Aleksandar Prodić
    • 3
  • Dragan Maksimović
    • 4
  1. 1.Department of Electronic EngineeringTechnical University of Catalunya (UPC BarcelonaTech)BarcelonaSpain
  2. 2.National SemiconductorsLongmontUSA
  3. 3.Electrical and Computer Engineering DepartmentUniversity of TorontoTorontoCanada
  4. 4.Department of Electrical and Computer EngineeringUniversity of ColoradoBoulderUSA

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