Semantics of DFCharts

Chapter

Abstract

In this chapter we present the formal semantics of DFCharts. Section 4.1 discusses the automata semantics, introduced first in [88], where the behaviour of a complete specification is expressed as an FSM. This section is divided into seven sub-sections Section 4.1.1 introduces multiclock FSMs that are used as inputs to DFCharts operators. Sections 4.1.2–4.1.5 define the semantics of four DFCharts operators: synchronous parallel, asynchronous parallel, localization\hiding and refinement. DFCharts operators are defined in a similar style as Argos [24] operators. However, because of the use of multiclock FSMs, their operation is quite different. Section 4.1.6 defines with a simple language how the operators may be applied on multiclock FSMs. As seen in Chap. 3, an SDFG and an FSM are connected with the asynchronous parallel operator. According to the semantics of the asynchronous parallel operator in Sect. 4.1.3, it operates only on FSMs like all other operators. For this reason, an SDFG is represented as an FSM so that it can be combined with “real FSMs”. This is the topic of Sect. 4.1.7. Since an SDFG proceeds at its own speeds, an FSM that represents an SDFG (“SDF FSM”) is triggered by a clock that is different from the clock of real FSMs. Thus, when a “real FSM” and “SDF FSM” are combined, a multiclock FSM results. In the definitions of operators, which comprise DFCharts automata semantics, rendezvous is treated simply as an event that triggers a transition. What exactly happens on the channel is irrelevant. This is the topic of Sect. 4.2. It examines in detail the ordering of events on a channel within the Tagged Signal Model (TSM) framework. The analysis leads to understanding of how an array variable produces multiple SDF tokens and vice versa. Data transfer from SDF to FSM is the topic of Sect. 4.2.1, while Sect. 4.2.2. deals with data transfer from FSM to SDF. The TSM semantics of DFCharts was previously described in [89]. Finally, Sect. 4.3 examines the effect of clock speeds on DFCharts behaviour.

Keywords

Parallel Operator Clock Speed Denotational Semantic Refinement Operator Dataflow Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 13.
    C.A.R. Hoare, Communicating sequential processes. Commun. ACM 21(8), 666–677 (1978)MathSciNetMATHCrossRefGoogle Scholar
  2. 14.
    R. Milner, Communication and Concurrency (Prentice-Hall, Englewood Cliffs, 1989)MATHGoogle Scholar
  3. 18.
  4. 24.
    F. Maraninchi, Y. Remond, Argos: an automaton-based synchronous language. Comput. Lang. 27(1–3), 61–92 (2001)MATHCrossRefGoogle Scholar
  5. 25.
    E.A. Lee, A. Sangiovanni-Vincentelli, A framework for comparing models of computation. IEEE Trans. Comput. Aided Des. Circ. Syst. 17(12), 1217–1229 (1998)CrossRefGoogle Scholar
  6. 39.
    S. Stuijk, M. Geilen, T. Basten, Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs, in Proceedings of Design Automation Conference (DAC ’06), San Francisco, July 2006Google Scholar
  7. 58.
    Esterel v7 reference manual, available from www.esterel-technologies.com
  8. 88.
    I. Radojevic, Z. Salcic, P. Roop, Design of heterogeneous embedded systems using DFCharts model of computation, in Proceedings of VLSI Design, Hyderabad, 3–7 Jan 2006Google Scholar
  9. 89.
    I. Radojevic, Z. Salcic, P. Roop, Modeling heterogeneous embedded systems in DFCharts, in Proceedings of Forum on Design and Specification Languages (FDL), Lausanne, 27–30 Sept 2005Google Scholar
  10. 90.
    M. Hennessy, H. Lin, Symbolic bisimulations. Theor. Comput. Sci. 138(2), 353–389 (1995)MathSciNetMATHCrossRefGoogle Scholar
  11. 91.
    R. Alur, D. Dill, A theory of timed automata. Theor. Comput. Sci. 126(2), 183–235 (1994)MathSciNetMATHCrossRefGoogle Scholar
  12. 92.
    S. Ramesh, Communicating reactive state machines: design, model and implementation, in IFAC Workshop on Distributed Computer Control Systems (Pergamon Press, Oxford, 1998)Google Scholar
  13. 93.
    S. Ramesh, Implementation of communicating reactive processes. Parallel Comput. 25(6), 703–727 (1999)MATHCrossRefGoogle Scholar
  14. 94.
    G. Berry, E. Sentovich, Multiclock Esterel, in Proceedings of Correct Hardware Design and Verification Methods (CHARME), LNCS 2144, Sept 2001Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Defence Technology AgencyNew Zealand Defence ForceAucklandNew Zealand
  2. 2.Computer Systems EngineeringUniversity of AucklandAucklandNew Zealand

Personalised recommendations