A Scalable Bandwidth-Aware Architecture for Connected Component Labeling
This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
KeywordsHardware Implementation Entry Register Connected Region Foreground Pixel Memory Subsystem
This work was supported in part by NSF awards #0702617 & #0916887, and a scholarship funding from the Government of the Sultanate of Oman.
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