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Parallel Transistor-Level Circuit Simulation

  • Eric R. Keiter
  • Heidi K. Thornquist
  • Robert J. Hoekstra
  • Thomas V. Russo
  • Richard L. Schiek
  • Eric L. Rankin

Abstract

With the advent of multi-core technology, inexpensive large-scale parallel platforms are now widely available. While this presents new opportunities for the EDA community, traditional transistor-level, SPICE-style circuit simulation has unique parallel simulation challenges. Here the Xyce Parallel Circuit Simulator is described, which has been designed from the “from-the-ground-up” to be distributed memory-parallel. Xyce has demonstrated scalable circuit simulation on hundreds of processors, but doing so required a comprehensive parallel strategy. This included the development of new solver technologies, including novel preconditioned iterative solvers, as well as attention to other aspects of the simulation such as parallel file I/O, and efficient load balancing of device evaluations and linear systems. Xyce relies primarily upon a message-passing (MPI-based) implementation, but optimal scalability on multi-core platforms can require a combination of message-passing and threading. To accommodate future parallel platforms, software abstractions allowing adaptation to other parallel paradigms are part of the Xyce design.

Keywords

Load Balance Domain Decomposition Linear Solver Iterative Solver Circuit Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Eric R. Keiter
    • 1
  • Heidi K. Thornquist
    • 1
  • Robert J. Hoekstra
    • 2
  • Thomas V. Russo
    • 1
  • Richard L. Schiek
    • 1
  • Eric L. Rankin
    • 1
  1. 1.Electrical and Microsystems Modeling DepartmentSandia National LaboratoriesAlbuquerqueUSA
  2. 2.Applied Mathematics & Applications DepartmentSandia National LaboratoriesAlbuquerqueUSA

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