Time-Interleaving: Multiplying the Speed of the ADC

Chapter
First Online:
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

While the current minimum feature size of IC fabrication technology limits the maximum achievable speed of electronic devices, parallel or time-interleaved (TI) architectures are one of the most effective solutions to boost the maximum speed of analog interfaces at the system level [1–7]. In principle the operating speed of the TI-ADC can grow linearly by increasing the number of parallel ADC channels, however various types of mismatches among different channels create modulation tones which degrade the performance of the TI-ADC, like offset [8, 9], gain [8, 9], timing [5, 8–11] as well as bandwidth mismatches (from the sampling RC time-constant) [9, 12–14]. Those mismatch effects must be fully characterized to achieve satisfactory performance in the design of TI-ADCs.

Keywords

Mismatch Error Mismatch Effect Sampling Clock Early Design Phase Capacitor Mismatch 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Faculty of Science and Technology Dept of Electrical and Electronics EnginUniversity of MacauMacaoChina, People’s Republic
  2. 2.Faculty of Science and Technology Dept of Electrical and Electronics EnginUniversity of Macau and Tech. Univ.of LisMacaoChina, People’s Republic

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