Compact Modeling of Double-Gate and Nanowire MOSFETs

Abstract

This chapter reviews recent developments on compact modeling of double-gate and nanowire MOSFETs. It starts with the core, long-channel drain current models of double-gate and nanowire MOSFETs, derived from the analytic solutions of 1-D Poisson and current continuity equations in Cartesian and cylindrical coordinates, respectively. Explicit and continuous solutions to the implicit parameters in both models have been developed. The short-channel models based on the scale length approach to the boundary value problems of 2-D Poisson’s equation in subthreshold are then described, followed by charge and capacitance models for both double-gate and nanowire MOSFETs. A popular, surface-potential based current expression in the literature is examined before concluding the chapter.

References

  1. 1.
    Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9, 927–937 (1966) CrossRefGoogle Scholar
  2. 2.
    Brews, J.R.: A charge sheet model of the MOSFET. Solid-State Electron. 21(2), 345–355 (1978) CrossRefGoogle Scholar
  3. 3.
    Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: An advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices ED-53, 1979–1993 (2006) CrossRefGoogle Scholar
  4. 4.
    Taur, Y.: An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Device Lett. 21(5), 245–247 (2000) CrossRefGoogle Scholar
  5. 5.
    Taur, Y., Liang, X., Wang, W., Lu, H.: A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Lett. 25(2), 107–109 (2004) CrossRefGoogle Scholar
  6. 6.
    Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices, 2nd edn. Cambridge Univ. Press, Cambridge (2009) Google Scholar
  7. 7.
    Lu, X., Lu, W.-Y., Taur, Y.: Effect of body doping on double-gate MOSFET characteristics. Semicond. Sci. Technol. 22, 252835 (2008) (6pp) Google Scholar
  8. 8.
    Jimenez, D., Iniguez, B., Sune, J., Marsal, L.F., Pallares, J., Roig, J., Flores, D.: Continuous analytic I-V model for surrounding-gate MOSFETs. IEEE Electron Device Lett. 25(8), 571–573 (2004) CrossRefGoogle Scholar
  9. 9.
    Yu, B., Lu, H., Liu, M., Taur, Y.: Explicit continuous models for double-gate and surrounding-gate MOSFETs. IEEE Trans. Electron Devices 54(10), 2715–2722 (2007) CrossRefGoogle Scholar
  10. 10.
    Chen, T.L., Gildenblat, G.: Analytical approximation for the MOSFET surface potential. Solid State Electron. 45(2), 335–339 (2001) CrossRefGoogle Scholar
  11. 11.
    Liang, X., Taur, Y.: A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans. Electron Devices 51(9), 1385–1391 (2004) CrossRefGoogle Scholar
  12. 12.
    Oh, S.-H., Monroe, D., Hergenrother, J.M.: Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Device Lett. 9, 445–447 (2000) Google Scholar
  13. 13.
    Frank, D.J., Taur, Y., Wong, H.-S.P.: Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Device Lett. 19, 385–387 (1998) CrossRefGoogle Scholar
  14. 14.
    Yu, B., Wang, L., Yuan, Y., Asbeck, P.M., Taur, Y.: Scaling of nanowire transistors. IEEE Trans. Electron Devices 55, 2846–2858 (2008) CrossRefGoogle Scholar
  15. 15.
    Yu, B., Yuan, Y., Song, J., Taur, Y.: A two-dimensional analytical solution for short-channel effects in nanowire MOSFETs. IEEE Trans. Electron Devices 56, 2357–2362 (2009) MathSciNetCrossRefGoogle Scholar
  16. 16.
    Ward, D., Dutton, R.: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits SC-13(5), 703–708 (1978) CrossRefGoogle Scholar
  17. 17.
    Lu, H., Taur, Y.: An analytic potential model for symmetric and asymmetric DG MOSFETs. IEEE Trans. Electron Devices 53(5), 1161–1168 (2006) CrossRefGoogle Scholar
  18. 18.
    Yu, B., Lu, W.-Y., Lu, H., Taur, Y.: Analytic charge model for surrounding-gate MOSFETs. IEEE Trans. Electron Devices 54(3), 492–496 (2007) CrossRefGoogle Scholar
  19. 19.
    Taur, Y., Richards, P.L.: Parametric amplification and oscillation at 36 GHz using a point-contact Josephson junction. J. Appl. Phys. 48(3), 1321–1326 (1977) CrossRefGoogle Scholar
  20. 20.
    Taur, Y., Kerr, A.R.: Low-noise Josephson mixers at 115 GHz using recyclable point contacts. Appl. Phys. Lett. 32(11), 775–777 (1978) CrossRefGoogle Scholar
  21. 21.
    Dunga, M.V., Lin, C.-H., Xi, X., Lu, D.D., Niknejad, A.M., Hu, C.: Modeling advanced FET technology in a compact model. IEEE Trans. Electron Devices 53(9), 1971–1978 (2006) CrossRefGoogle Scholar
  22. 22.
    Smit, G.D.J., Scholten, A.J., Curatola, G., van Langevelde, R., Gildenblat, G., Klaassen, D.B.M.: PSP-based scalable compact FinFET model. In: NTSI-Nanotech 2007, vol. 3, pp. 520–525 (2007) Google Scholar
  23. 23.
    Sallese, J.-M., Krummenacher, F., Pregaldiny, F., Lallement, C., Roy, A., Enz, C.: A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electron. 49(3), 485–489 (2005) CrossRefGoogle Scholar
  24. 24.
    Lu, H., Yu, B., Taur, Y.: A unified charge model for symmetric double-gate and surrounding-gate MOSFETs. Solid-State Electron. 52(1), 67–72 (2008) CrossRefGoogle Scholar
  25. 25.
    Song, J., Yu, B., Yuan, Y., Taur, Y.: A review on compact modeling of multiple-Gate MOSFETs. IEEE Trans. Circuits Syst. I 56(8), 1858–1869 (2009) MathSciNetCrossRefGoogle Scholar
  26. 26.
    Dessai, G., Dey, A., Gildenblat, G., Smit, G.D.J.: Symmetric linearization method for double-gate and surrounding-gate MOSFET model. Solid-State Electron. 53(5), 548–556 (2009) CrossRefGoogle Scholar
  27. 27.
    Ortiz-Conde, A., Garcia-Sanchez, F.J., Muci, J., Malobabic, S., Liou, J.J.: A review of core compact models for undoped double-gate SOI MOSFETs. IEEE Trans. Electron Devices 54(1), 131–140 (2007) CrossRefGoogle Scholar
  28. 28.
    Song, J., Yu, B., Xiong, W., Hsu, C.H., Cleavelin, C.R., Ma, M., Patruno, P., Taur, Y.: Experimental hardware calibrated compact models for 50 nm n-channel FinFETs. In: Conf. SOI, 2007 IEEE, pp. 131–132 (2007) Google Scholar
  29. 29.
    Yu, B., Song, J., Yuan, Y., Taur, Y.: A unified analytic drain current model for multiple-gate MOSFETs. IEEE Trans. Electron Devices 55(8), 2157–2163 (2008) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.University of CaliforniaSan DiegoUSA

Personalised recommendations