Abstract
As the scaling of conventional planar CMOS is reaching its limits, multiple-gate CMOS structures will likely take up the baton. To facilitate circuit simulation in such advanced technologies, we have developed BSIM-MG: a versatile compact model for multi-gate MOSFETs. In this chapter separate formulations for common multi-gate and independent multi-gate MOSFETs are presented. The core I-V and C-V models are derived and agree well with TCAD simulations without using fitting parameters, reflecting the predictivity and scalability of the model. Physical effects such as volume inversion, short channel effects and quantum mechanical effects are included in the model. We verify BSIM-MG against triple-gate SOI FinFET experimental data. The model fits data very well across a wide range of biases, gate lengths and temperatures. It is also computationally efficient and suitable for simulating large circuits. Finally, several multi-gate circuit simulation examples are presented to demonstrate the use of the model.
Keywords
SRAM Cell Short Channel Effect Equivalent Oxide Thickness Static Noise Margin TCAD SimulationNotes
Acknowledgments
We would like to express our sincere appreciation to Dr. Mohan Dunga for his pioneering development of BSIM-IMG and BSIM-CMG. We would also like to thank Dr. Weize Xiong and Dr. Rinn Cleavelin at Texas Instrument, Dr. Paul Patruno at SOITEC, Dr. Jiunn-Ren Hwang and Dr. Fu-Liang Yang at Taiwan Semiconductor Manufacturing Corporation for generously sharing their measured FinFET data. The work presented in this chapter would not have been possible without the funding support by Semiconductor Research Corporation (Task ID: 1451.001) and IMPACT, UC Discovery, and its industrial sponsors.
References
- 1.Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.-S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89, 259–288 (2001) CrossRefGoogle Scholar
- 2.Assaderaghi, F., Sinitsky, D., Bokor, J., Ko, P.K., Gaw, H., Hu, C.: High-field transport of inversion-layer electrons and holes including velocity overshoot. IEEE Trans. Electron Devices 44, 664–671 (1997) CrossRefGoogle Scholar
- 3.Lundstrom, M.: Elementary scattering theory of the Si MOSFET. IEEE Electron Device Lett. 18, 361–363 (1997) CrossRefGoogle Scholar
- 4.Ghani, T., et al.: A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 407–410 (2003) Google Scholar
- 5.Lee, W.-C., Hu, C.: Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling. IEEE Trans. Electron Devices 48, 1366–1373 (2001) CrossRefGoogle Scholar
- 6.Mistry, K., et al.: 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 247–250 (2007) Google Scholar
- 7.Colinge, J.-P.: FinFETs and Other Multi-gate Transistors. Springer, Berlin (2008) CrossRefGoogle Scholar
- 8.Asenov, A.: Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 m MOSFET’s: a 3-D “atomistic” simulation study. IEEE Trans. Electron Devices 45, 2505–2513 (1998) CrossRefGoogle Scholar
- 9.Kim, H.-S., Lee, S.-B., Choi, D.-U., Shim, J.-H., Lee, K.-H., Lee, K.-P., Kim, K.-N., Park, J.-W.: A high-performance 16M DRAM on a thin film SOI. In: Digest of Technical Papers, Symposium on VLSI Technology, pp. 143–144 (1995) Google Scholar
- 10.Huang, X., Lee, W.-C., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.-J., Bokor, J., Hu, C.: Sub 50-nm FinFET: PMOS. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 67–70 (1999) Google Scholar
- 11.Hu, C.: MOSFETs in ICs–scaling, leakage, and other topics. In: Modern Semiconductor Devices for Integrated Circuits. Prentice Hall, New York (2009) Google Scholar
- 12.Yang, F.-L., Chen, H.-Y., Chen, F.-C., Chan, Y.-L., Yang, K.-N., Chen, C.-J., Tao, H.-J., Choi, Y.-K., Liang, M.-S., Hu, C.: 35 nm CMOS FinFETs. In: Digest of Technical Papers, Symposium on VLSI Technology, pp. 104–105 (2002) Google Scholar
- 13.von Arnim, K., et al.: A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM. In: Digest of Technical Papers, Symposium on VLSI Technology, pp. 106–107 (2007) Google Scholar
- 14.Kedzierski, J., et al.: Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 247–250 (2002) Google Scholar
- 15.Kavalieros, J., Doyle, B., Datta, S., Dewey, G., Doczy, M., Jin, B., Lionberger, D., Metz, M., Rachmady, W., Radosavljevic, M., Shah, U., Zelick, N., Chau, R.: Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering. In: Digest of Technical Papers, Symposium on VLSI Technology, pp. 50–51 (2006) Google Scholar
- 16.Sheu, B., Scharfetter, D.L., Ko, P.-K., Jeng, M.-C.: BSIM: Berkeley short-channel IGFET model for MOS transistors. IEEE J. Solid-State Circuits 22, 558–566 (1987) CrossRefGoogle Scholar
- 17.BSIM (Berkeley Short-channel IGFET Model). http://www-device.eecs.berkeley.edu/~bsim/
- 18.Su, P., Fung, S.K.H., Tang, S., Assaderaghi, F., Hu, C.: BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. In: Proc. of the IEEE Custom Integrated Circuits Conference, pp. 197–200 (2000) Google Scholar
- 19.Chan, M., Su, P., Wan, H., Lin, C.-H., Fung, S.K.-H., Niknejad, A.M., Hu, C., Ko, P.K.: Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs. Solid-State Electron. 48, 969–978 (2004) CrossRefGoogle Scholar
- 20.Dunga, M.V., Lin, C.-H., Lu, D.D., Xiong, W., Cleavelin, C.R., Patruno, P., Hwang, J.-R., Yang, F.-L., Niknejad, A.M., Hu, C.: BSIM-MG: A versatile multi-gate FET model for mixed-signal design. In: Digest of Technical Papers, Symposium on VLSI Technology, pp. 60–61 (2007) Google Scholar
- 21.Lu, D.D., Dunga, M.V., Lin, C.-H., Niknejad, A.M., Hu, C.: A multi-gate MOSFET compact model featuring independent-gate operation. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 565–568 (2007) Google Scholar
- 22.Fossum, J.G., Ge, L., Chiang, M.-H., Trivedi, V.P., Chowdhury, M.M., Matthew, L., Workman, G.O., Nguyen, B.-Y.: A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electron. 48, 919–926 (2004) CrossRefGoogle Scholar
- 23.Yu, B., Song, J., Yuan, Y., Lu, W.-Y., Taur, Y.: A unified analytic Drain V Current model for multiple-gate MOSFETs. IEEE Trans. Electron Devices 55, 2157–2163 (2008) CrossRefGoogle Scholar
- 24.Dessai, G., Dey, A., Gildenblat, G., Smit, G.D.J.: Symmetric linearization method for double-gate and surrounding-gate MOSFET models. Solid-State Electron. 53, 548–556 (2009) CrossRefGoogle Scholar
- 25.Sallese, J.-M., Krummenacher, F., Pregaldiny, F., Lallement, C., Roy, A., Enz, C.: A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism. Solid-State Electron. 49, 485–489 (2005) CrossRefGoogle Scholar
- 26.Pei, G., Ni, W., Kammula, A.V., Minch, B.A., Kan, E.C.-C.: Physical compact model of DG MOSFET for mixed-signal circuit applications—Part I: model description. IEEE Trans. Electron Devices 50, 2135–2143 (2003) CrossRefGoogle Scholar
- 27.Ishimura, K., Sadachika, N., Kusu, S., Miura-Mattausch, M.: Compact model HiSIM-DG both for symmetrical and asymmetrical DG-MOSFET structures. In: Proc. Workshop on Compact Modeling (2009) Google Scholar
- 28.International Technology Roadmap for Semiconductors. http://www.itrs.net/
- 29.Takayanagi, K., Kondo, Y., Ohnishi, H.: Suspended gold nanowires: ballistic transport of electrons. J. Jpn. Soc. Appl. Phys. Int. (JSAPI) 3, 3–8 (2001) Google Scholar
- 30.Fried, D., Duster, J.S., Kornegay, K.T.: High-performance p-type independent-gate FinFETs. IEEE Electron Device Lett. 25, 199–201 (2004) CrossRefGoogle Scholar
- 31.Yang, I.Y., Vieri, C., Chandrakasan, A., Antoniadis, D.A.: Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices 44, 822–831 (1997) CrossRefGoogle Scholar
- 32.Liu, H., Taur, Y.: An analytic potential model for symmetric and asymmetric DG MOSFETs. IEEE Trans. Electron Devices, 1161–1168 (2006) Google Scholar
- 33.Dunga, M.V., Lin, C.-H., Niknejad, A.M., Hu, C.: BSIM-CMG: a compact model for multi-gate transistors. In: FinFETs and Other Multi-gate Transistors, pp. 113–153 (2008) Google Scholar
- 34.Lu, D.D.: Efficient surface potential calculation for the asymmetric independent double-gate MOSFET. UC Berkeley Master’s Report (2007) Google Scholar
- 35.Brews, J.R.: A charge-sheet model of the MOSFET. Solid-Sate Electron. 21, 345–355 (1978) CrossRefGoogle Scholar
- 36.Synopsys Inc.: Taurus Process and Device User Manual (2003) Google Scholar
- 37.Oh, S.-Y., Ward, D.E., Dutton, R.W.: Transient analysis of MOS transistors. IEEE Trans. Electron Devices 27, 1571–1578 (1980) CrossRefGoogle Scholar
- 38.Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. Oxford (1999) Google Scholar
- 39.Venugopolan, S.: A Compact Model for Cylindrical Gate MOSFET for circuit simulations. UC Berkeley Master’s Report (2010) Google Scholar
- 40.Dunga, M.V.: Nanoscale CMOS modeling. Ph.D. Thesis, UC Berkeley (2007) Google Scholar
- 41.Dunga, M.V., Lin, C.-H., Xi, X., Lu, D.D., Niknejad, A.M., Hu, C.: Modeling advanced FET technology in a compact model (invited). IEEE Trans. Electron Devices 53, 1971–1978 (2006) CrossRefGoogle Scholar
- 42.Taur, Y.: An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Device Lett. 21, 245–247 (2000) CrossRefGoogle Scholar
- 43.Sebah, P., Gourdon, X.: Newton’s method and high order iterations (2001). http://numbers.computation.free.fr/Constants/Algorithms/newton.ps
- 44.Trivedi, V.P., Fossum, J.G.: Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs. IEEE Electron Device Lett. 26, 579–582 (2005) CrossRefGoogle Scholar
- 45.Lin, C.-H.: Compact modeling of nanoscale CMOS. Ph.D. Thesis, UC Berkeley (2007) Google Scholar
- 46.Liu, Z.-H., Hu, C., Huang, J.-H., Chan, T.-Y., Jeng, M.-C., Ko, P.K., Cheng, Y.C.: Threshold voltage model for deep-submicrometer MOSFET’s. IEEE Trans. Electron Devices 40, 86–95 (1993) CrossRefGoogle Scholar
- 47.BSIM4 User’s Manual. http://www-device.eecs.berkeley.edu/~bsim3/bsim4_get.html
- 48.BSIMSOI User’s Manual. http://www-device.eecs.berkeley.edu/~bsimsoi/get.html
- 49.Suzuki, K., Sugii, T.: Analytical models for n+-p+ double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 42, 1940–1948 (1995) CrossRefGoogle Scholar
- 50.Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., Kan, E.C.-C.: FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans. Electron Devices 49, 1411–1419 (2002) CrossRefGoogle Scholar
- 51.Jin, W., Fung, S.K.H., Liu, W., Chan, P.C.H., Hu, C.: Self-heating characterization for SOI MOSFET based on AC output conductance. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 175–178 (1999) Google Scholar
- 52.Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.: A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors. IEEE Trans. Electron Devices 37, 654–665 (1990) CrossRefGoogle Scholar
- 53.Cao, K.M., Lee, W.-C., Liu, W., Jin, X., Su, P., Fung, S.K.H., An, J.X., Yu, B., Hu, C.: BSIM4 gate leakage model including source-drain partition. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 815–818 (2000) Google Scholar
- 54.Wann, H.-J., Ko, P.K., Hu, C.: Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: Technical Digest, IEEE International Electron Devices Meeting, pp. 147–150 (1992) Google Scholar
- 55.Yao, S., Morshed, T.H., Lu, D.D., Venugopalan, S., Niknejad, A.M., Hu, C.: A global parameter extraction procedure for multi-gate MOSFETs. To Be Presented in the 23rd International Conference on Microelectronic Test Structures (2010) Google Scholar
- 56.Cheng, Y., Hu, C.: MOSFET Modeling and BSIM3 User’s Guide. Springer, Berlin (1999) Google Scholar
- 57.Banna, S.R., Chan, P.C.H., Ko, P.K., Nguyen, C.T., Chan, M.: Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET’s. IEEE Trans. Electron Devices 42, 1949–1955 (1995) CrossRefGoogle Scholar
- 58.Guo, Z., Balasubramanian, S., Zlatanovici, R., King, T.-J., Nikolić, B.: FinFET-based SRAM design. In: International Symposium on Low Power Electronics and Design (ISLPED), pp. 2–7 (2005) Google Scholar
- 59.Oldiges, P., Lin, Q., Petrillo, K., Sanchez, M., Ieong, M., Hargrove, M.: Modeling line edge roughness effects in sub 100 nanometer gate length devices. In: Proc. Int. Conference on Simulation of Semiconductor Devices and Processes (SISPAD), pp. 131–134 (2000) Google Scholar
- 60.Lu, D.D., Lin, C.-H., Yao, S., Xiong, W., Bauer, F., Cleavelin, C.R., Niknejad, A.M., Hu, C.: Design of FinFET SRAM cells using a statistical compact model. In: Proc. Int. Conference on Simulation of Semiconductor Devices and Processes (SISPAD), pp. 127–130 (2009) Google Scholar
- 61.Lin, C.-H., Dunga, M.V., Lu, D.D., Niknejad, A.M., Hu, C.: Performance-aware corner model for design for manufacturing. IEEE Trans. Electron Devices 56, 595–600 (2009) CrossRefGoogle Scholar