Dynamically Reconfigurable Systems for Wireless Sensor Networks

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Abstract

In this chapter, we explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which applies frequent runtime reconfiguration to obtain the required combination of high energy efficiency and programmability for the target domain. We particularly examine the effect of the reconfiguration overhead on total system efficiency, and propose a novel reconfiguration mechanism to reduce this overhead. Comparing the energy consumption, area, and performance of our architecture to processor and ASIC designs, our experiments show the low total energy consumption achieved, the low reconfiguration overhead, and the specific region of the architecture in the design space between processors and ASICs. In particular, large energy-savings of factor 2 to 6 and speed-ups of factor 6 to 14 compared to processors are obtained on average. Overall, our work shows the high suitability of frequent runtime reconfiguration for the design of very energy efficient but yet programmable embedded system architectures.

Keywords

Sensor Node Wireless Sensor Network Medium Access Control Clock Cycle Data Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Institute of Microelectronic SystemsTechnische Universität DarmstadtDarmstadtGermany

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