Designing of DPA Resistant Circuit Using Secure Differential Logic Gates

Conference paper
First Online:
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 410)

Abstract

Crypto circuits can be attacked using the technique of differential power analysis by another/separate party, using power consumption dependence on secret message/information for extracting the critical data (information). To avoid DPA (Differential Power Analysis) and security bases, differential logic styles are basically used, because of constant power dissipation. This paper proposes a new design methodology using OR-NOR gates in 90 nm VLSI technology using SABL (Sense Amplifier Based Logic) for DPDN (Differential Pull down Logic) to secure/protect differential logic gates and to eliminate charge in the pull-down differential gate and to remove the memory effect.

Keywords

Sense amplifier based logic Differential Power Analysis Differential Pull Down Network Universal logic gates 90 nm VLSI technology 
This is a preview of subscription content, log in to check access.

References

  1. 1.
    Tena-Sánchez, E., Castro, J., Acosta, A.J.: A methodology for optimized design of secure differential logic gates for DPA resistant circuits. IEEE J. Emerg. Sel. Top. Circuits Syst. 4(2), 203–215 (2014)CrossRefGoogle Scholar
  2. 2.
    Gutmann, P., Naccache, D., Palmer, C.C.: Side-channel attacks on cryptographic software. IEEE J. Co-published Comput. Reliab. Soc. 9, 1540–7993 (2009)Google Scholar
  3. 3.
    Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Proceedings of the International Cryptal Conference, pp. 388–397. (1999)Google Scholar
  4. 4.
    Tiri, K., Akmal, M., Verbau Whede, I.: A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In: Proceedings of the European Solid-State Circuits Conference, pp. 403–406. (2002)Google Scholar
  5. 5.
    Hassoune, I., Macé, F., Flandre, D., Legat, J.-D.: Low-swing current mode logic (LSCML): a new logic style for secure and robust smart cards against power analysis attacks. Micro Electron. J. 37(9), 997–1006 (2006)Google Scholar
  6. 6.
    Allam, M.W., Elmasry, M.I.: Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE J. Solid-State Circuits 36(3), 550–558 (2001)CrossRefGoogle Scholar
  7. 7.
    Bucci, M., Giancane, L., Luzzi, R., Trifiletti, A.: Three-phase dual rail pre-charge logic. In: Proceedings of the International Workshop Cryptography. Hardware Embedded Systems, pp. 232–24. (2006)Google Scholar
  8. 8.
    Suzuki, D., Saeki, M.: Security evaluation of DPA countermeasures using dual-rail pre-charge logic style. In: Proceedings of the International Workshop Cryptography. Hardware Embedded Systems, pp. 255–269. (2006)Google Scholar
  9. 9.
    Lin, L., Burleson, W.: Leakage-based differential power analysis (LDPA) on sub-90 nm CMOS crypto systems. In: Proceedings of the IEEE International Symposium Circuits Systems, pp. 252–255. (2008)Google Scholar
  10. 10.
    Tiri, K., Verbau Whede, I.: Design method for constant power consumption of differential logic circuits. In: Proceedings of Design, Automat. Test European Conference on Exhibit, pp. 1530–1591. (2005)Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringGMR Institute of TechnologyRajamIndia

Personalised recommendations