Design of Row Decoder Circuit for Semiconductor Memory at Low Power and Small Delay Using MOS Transistor at Nano Dimension Channel Length

Conference paper
First Online:
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 335)

Abstract

Row decoder is used to decode the address locations of memory. In this paper designing and power–delay analysis of 2–4 row decoder based on MOS transistor at channel length of 150 nm have been presented. Value of power supply voltage (V dd) has been varied from 0.4 to 1.2 V to plot the variation of power consumption and delay for decoding the rows. According to simulation delay and power consumption are of the order of 10−11 s and 10−4 W, respectively. Tanner Spice (T-SPICE) software has been used to simulate the design.

Keywords

Row decoder Memory Power Delay MOS T-SPICE 
This is a preview of subscription content, log in to check access.

References

  1. 1.
    S.M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design (Tata McGraw-Hill, New Delhi, 2003)Google Scholar
  2. 2.
    J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits A Design ersptive (Pearson Education, 2005)Google Scholar
  3. 3.
    R. Jacob Baker, H.W. Li, D. Boyce, CMOS Circuit Design, Layout, and Simulation (PHI, New Delhi, 2003)Google Scholar
  4. 4.
    J. Uyemura, Introduction to VLSI Circuits and Systems (India, 2007)Google Scholar
  5. 5.
    M.H. Rashid, Introduction to PSpice using OrCad for Circuits and Electronics (PHI, New Delhi, 2005)Google Scholar
  6. 6.
    K. Sasaki, S. Hanamura, K. Ueda, T. Oono, O. Minato, Y. Sakai, S. Meguro, M. Tsunematsu, T. Masuhara, M. Kubotera, H. Toyoshima, A 15-ns 1-Mbit CMOS SRAM. IEEE J. Solid-State Circuits 23(5), 1067–1072 (1988)Google Scholar
  7. 7.
    T. Kobayashi, K. Arimoto, Y. Ikeda, M. Hatanaka, K. Mashiko, M. Yamada, T. Nakano, A high-speed 64 K × 4 CMOS DRAM using on-chip self-timing techniques. IEEE J. Solid-State Circuits 21(5), 655–661 (1986)Google Scholar
  8. 8.
    G. Samson, N. Ananthapadmanabhan, S.A. Badrudduza, L.T. Clark, Low-power dynamic memory word line decoding for static random access memories. IEEE J. Solid-State Circuits 43, 2524–2532 (2008)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Electronics and Communication Engineering DepartmentNarula Institute of TechnologyKolkataIndia

Personalised recommendations