Economic Evaluation of Alternatives for Microelectronics Lithography Processing

Abstract

Cost-of-Ownership models for microelectronics fabrication equipment have been adapted to the analysis of the economics of optical lithography and associated processes such as mask making and photoresist application. This requires modification of the cost-of-ownership approach to the series of processing steps for wafer fabrication. These models enable the economic impacts of microelectronics design and processing decisions on silicon wafer fabrication to be estimated. The models have been incorporated into a software tool that uses defaults and data based on current industry standards and practice. Using this program the sensitivity of wafer processing costs to basic integrated circuit design parameters can be evaluated. The basic assumptions and data used in the economic models are presented together with results from application to typical case studies. The availability of these models facilitates the design for manufacture of microelectronic integrated circuits.