Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

  • Yiming Li
  • Jam-Wem Lee
  • Hong-Mu Chou
Conference paper

Abstract

In this paper, electrical characteristics of nanoscale single-, double-, and all-around-gate silicon-On-insulator (SOI) devices are computational investigated by using a quantum mechanical simulation. Considering several important properties, such as on/off current ratio, drain induced channel barrier height lowering, threshold voltage roll off, and subthreshold swing, geometry aspect ratio is systematically calculated and characterized among structures. To obtain good operation characteristics, the ratio of channel length and silicon film thickness should be optimized with respect to device structures.

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References

  1. [1]
    H. Wakabayashi et al., “Sub-10-nm planar-bulk-CMOS devices using lateral junction control”, Tech. Dig. IEDM, p. 20.7, 2003.Google Scholar
  2. [2]
    M. Ogawa et al., “Quantum transport modeling in nano-scale devices”, Proc. IEEE SISPAD, pp. 261–266, 2002.Google Scholar
  3. [3]
    M. Ieong et al., “High performance double-gate device technology challenges and opportunities”, Proc. IEEE ISQED, pp. 492–495, 2002.Google Scholar
  4. [4]
    X. Huang et al., “Sub 50-nm FinFET: PMOS”, Tech. Dig. IEDM, pp. 67–70, 1999.Google Scholar
  5. [5]
    Y. Li et al., “Comparison of quantum correction models for ultratin oxide single-and doublegate MOS structures under the inversion conditions”, Proc. IEEE-Nano, pp. 36–39, 2003.Google Scholar
  6. [6]
    J. H. Rhew et al., “A numerical study of ballistic transport in a nanoscale MOSFET”, SolidState Elec. vol. 46, pp. 1899–1906, 2002.CrossRefGoogle Scholar
  7. [7]
    T. J. Walls et al., “MOSFETs below 10nm: quantum theory”, Physica E vol. 19, pp. 23–27, 2003.CrossRefGoogle Scholar
  8. [8]
    A. Asenov et al., “Quantum corrections in the simulation of decanano MOSFETs”, Solid-State Elec. vol. 47, pp. 1141–1145, 2003.CrossRefGoogle Scholar
  9. [9]
    V.A. Sverdlov et al., “Nanoscale silicon MOSFETs: A theoretical study”, IEEE Trans. ED vol. 50, 1926–1933,2003.CrossRefGoogle Scholar
  10. [10]
    A. Asenov et al., “The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices”, J. Comput. Elec. vol. 1, pp. 503–513, 2002.CrossRefGoogle Scholar
  11. [11]
    Y. Li et al., “Numerical Simulation of Quantum Effects in High-k Gate Dielectrics MOS Structures using Quantum Mechanical Models”, Comput. Phys. Commun., vol. 147, pp. 214–217, 2002.CrossRefGoogle Scholar
  12. [12]
    Y. Li et al., “A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation”, Eng. Comput., vol. 18, pp. 124–137, 2002.CrossRefGoogle Scholar
  13. [13]
    R. Venugopal et al., “Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches”, J. Appl. Phys., vol. 92, 3730–3739, 2002.CrossRefGoogle Scholar
  14. [14]
    Y. Naveh et al., “Modeling of 10-nm-scale ballistic MOSFET’s”, IEEE ED Lett., vol. 21, pp. 242–244, 2000.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Wien 2004

Authors and Affiliations

  • Yiming Li
    • 1
    • 2
  • Jam-Wem Lee
    • 1
  • Hong-Mu Chou
    • 3
  1. 1.Dept. of Computational NanoelectronicsNat’l Nano Device Lab.HsinchuTAIWAN
  2. 2.Microelectronics & Information Systems Research CenterNat’l Chiao Tung Univ.HsinchuTAIWAN
  3. 3.Dept. of ElectrophysicsNational Chiao Tung Univ.HsinchuTAIWAN

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