Side-Channel Analysis Protection and Low-Latency in Action

– Case Study of PRINCE and Midori –
  • Amir MoradiEmail author
  • Tobias Schneider
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10031)


During the last years, the industry sector showed particular interest in solutions which allow to encrypt and decrypt data within one clock cycle. Known as low-latency cryptography, such ciphers are desirable for pervasive applications with real-time security requirements. On the other hand, pervasive applications are very likely in control of the end user, and may operate in a hostile environment. Hence, in such scenarios it is necessary to provide security against side-channel analysis (SCA) attacks while still keeping the low-latency feature.

Since the single-clock-cycle concept requires an implementation in a fully-unrolled fashion, the application of masking schemes – as the most widely studied countermeasure – is not straightforward. The contribution of this work is to present and discuss about the difficulties and challenges that hardware engineers face when integrating SCA countermeasures into low-latency constructions. In addition to several design architectures, practical evaluations, and discussions about the problems and potential solutions with respect to the case study PRINCE (also compared with Midori), the final message of this paper is a couple of suggestions for future low-latency designs to – hopefully – ease the integration of SCA countermeasures.



The authors would like to acknowledge Ventzislav Nikov for his help with the decomposition process and Alexander Kühn for his help with implementation of different asynchronous variants of PRINCE on FPGA. The research in this work was supported in part by the DFG Research Training Group GRK 1817/1.

Supplementary material


  1. 1.
    Side-channel attack user reference architecture.
  2. 2.
    Balasch, J., Gierlichs, B., Verdult, R., Batina, L., Verbauwhede, I.: Power analysis of atmel cryptomemory – recovering keys from secure EEPROMs. In: Dunkelman, O. (ed.) CT-RSA 2012. LNCS, vol. 7178, pp. 19–34. Springer, Heidelberg (2012). doi: 10.1007/978-3-642-27954-6_2 CrossRefGoogle Scholar
  3. 3.
    Banik, S., Bogdanov, A., Isobe, T., Shibutani, K., Hiwatari, H., Akishita, T., Regazzoni, F.: Midori: a block cipher for low energy. In: Iwata, T., Cheon, J.H. (eds.) ASIACRYPT 2015. LNCS, vol. 9453, pp. 411–436. Springer, Heidelberg (2015). doi: 10.1007/978-3-662-48800-3_17 CrossRefGoogle Scholar
  4. 4.
    Banik, S., Bogdanov, A., Regazzoni, F.: Exploring energy efficiency of lightweight block ciphers. In: Dunkelman, O., Keliher, L. (eds.) SAC 2015. LNCS, vol. 9566, pp. 178–194. Springer, Heidelberg (2016). doi: 10.1007/978-3-319-31301-6_10 CrossRefGoogle Scholar
  5. 5.
    Bhasin, S., Guilley, S., Flament, F., Selmane, N., Danger, J.: Countering early evaluation: an approach towards robust dual-rail precharge logic. In: Workshop on Embedded Systems Security - WESS 2010, p. 6. ACM (2010)Google Scholar
  6. 6.
    Bhasin, S., Guilley, S., Sauvage, L., Danger, J.-L.: Unrolling cryptographic circuits: a simple countermeasure against side-channel attacks. In: Pieprzyk, J. (ed.) CT-RSA 2010. LNCS, vol. 5985, pp. 195–207. Springer, Heidelberg (2010). doi: 10.1007/978-3-642-11925-5_14 CrossRefGoogle Scholar
  7. 7.
    Bilgin, B., Gierlichs, B., Nikova, S., Nikov, V., Rijmen, V.: A more efficient AES threshold implementation. In: Pointcheval, D., Vergnaud, D. (eds.) AFRICACRYPT 2014. LNCS, vol. 8469, pp. 267–284. Springer, Heidelberg (2014). doi: 10.1007/978-3-319-06734-6_17 CrossRefGoogle Scholar
  8. 8.
    Bilgin, B., Gierlichs, B., Nikova, S., Nikov, V., Rijmen, V.: Higher-order threshold implementations. In: Sarkar, P., Iwata, T. (eds.) ASIACRYPT 2014. LNCS, vol. 8874, pp. 326–343. Springer, Heidelberg (2014). doi: 10.1007/978-3-662-45608-8_18 Google Scholar
  9. 9.
    Bilgin, B., Gierlichs, B., Nikova, S., Nikov, V., Rijmen, V.: Trade-offs for threshold implementations illustrated on AES. IEEE Trans. CAD Integr. Circ. Syst. 34(7), 1188–1200 (2015)CrossRefzbMATHGoogle Scholar
  10. 10.
    Bilgin, B., Nikova, S., Nikov, V., Rijmen, V., Stütz, G.: Threshold implementations of All 3\(\times \)3 and 4\(\times \)4 S-boxes. In: Prouff, E., Schaumont, P. (eds.) CHES 2012. LNCS, vol. 7428, pp. 76–91. Springer, Heidelberg (2012). doi: 10.1007/978-3-642-33027-8_5 CrossRefGoogle Scholar
  11. 11.
    Bilgin, B., Nikova, S., Nikov, V., Rijmen, V., Tokareva, N., Vitkup, V.: Threshold implementations of small S-boxes. Crypt. Commun. 7(1), 3–33 (2015)MathSciNetCrossRefzbMATHGoogle Scholar
  12. 12.
    Bogdanov, A., Knudsen, L.R., Leander, G., Paar, C., Poschmann, A., Robshaw, M.J.B., Seurin, Y., Vikkelsoe, C.: PRESENT: an ultra-lightweight block cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450–466. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-74735-2_31 CrossRefGoogle Scholar
  13. 13.
    Borghoff, J., Canteaut, A., Güneysu, T., Kavun, E.B., Knezevic, M., Knudsen, L.R., Leander, G., Nikov, V., Paar, C., Rechberger, C., Rombouts, P., Thomsen, S.S., Yalçın, T.: PRINCE – a low-latency block cipher for pervasive computing applications. In: Wang, X., Sako, K. (eds.) ASIACRYPT 2012. LNCS, vol. 7658, pp. 208–225. Springer, Heidelberg (2012). doi: 10.1007/978-3-642-34961-4_14 CrossRefGoogle Scholar
  14. 14.
    Bouesse, G., Renaudin, M., Witon, A., Germain, F.: A clock-less low-voltage AES crypto-processor. In: Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, pp. 403–406. IEEE (2005)Google Scholar
  15. 15.
    Bouesse, G.F., Renaudin, M., Dumont, S., Germain, F.: DPA on quasi delay insensitive asynchronous circuits: formalization and improvement. In: DATE, pp. 424–429. IEEE Computer Society (2005)Google Scholar
  16. 16.
    Bouesse, F., Renaudin, M., Sicard, G.: Improving DPA resistance of quasi delay insensitive circuits using randomly time-shifted acknowledgment signals. In: Reis, R., Osseiran, A., Pfleiderer, H.-J. (eds.) VLSI-SoC 2005. IIFIP, vol. 240, pp. 11–24. Springer, Heidelberg (2007). doi: 10.1007/978-0-387-73661-7_2 CrossRefGoogle Scholar
  17. 17.
    Bouesse, F., Sicard, G., Renaudin, M.: Path swapping method to improve DPA resistance of quasi delay insensitive asynchronous circuits. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 384–398. Springer, Heidelberg (2006). doi: 10.1007/11894063_30 CrossRefGoogle Scholar
  18. 18.
    Cooper, J., Demulder, E., Goodwill, G., Jaffe, J., Kenworthy, G., Rohatgi, P.: Test vector leakage assessment (TVLA) methodology in practice. In: International Cryptographic Module Conference (2013)Google Scholar
  19. 19.
    Dean, M.E., Williams, T.E., Dill, D.L.: Efficient self-timing with level-encoded 2-phase dual-rail (LEDR). In: Conference on Advanced Research in VLSI, pp. 55–70. MIT Press (1991)Google Scholar
  20. 20.
    Ding, A.A., Chen, C., Eisenbarth, T.: Simpler, faster, and more robust t-test based leakage detection. In: Standaert, F.-X., Oswald, E. (eds.) COSADE 2016. LNCS, vol. 9689, pp. 163–183. Springer, Heidelberg (2016). doi: 10.1007/978-3-319-43283-0_10 CrossRefGoogle Scholar
  21. 21.
    Durvaux, F., Standaert, F.-X., Del Pozo, S.M.: Towards easy leakage certification. In: Gierlichs, B., Poschmann, A.Y. (eds.) CHES 2016. LNCS, vol. 9813, pp. 40–60. Springer, Heidelberg (2016). doi: 10.1007/978-3-662-53140-2_3 CrossRefGoogle Scholar
  22. 22.
    Eisenbarth, T., Kasper, T., Moradi, A., Paar, C., Salmasizadeh, M., Shalmani, M.T.M.: On the power of power analysis in the real world: a complete break of the KeeLoq code hopping scheme. In: Wagner, D. (ed.) CRYPTO 2008. LNCS, vol. 5157, pp. 203–220. Springer, Heidelberg (2008). doi: 10.1007/978-3-540-85174-5_12 CrossRefGoogle Scholar
  23. 23.
    Fournier, J.J.A., Moore, S., Li, H., Mullins, R., Taylor, G.: Security evaluation of asynchronous circuits. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003). doi: 10.1007/978-3-540-45238-6_12 CrossRefGoogle Scholar
  24. 24.
    Goodwill, G., Jun, B., Jaffe, J., Rohatgi, P.: A testing methodology for side channel resistance validation. In: NIST non-invasive attack testing workshop (2011).
  25. 25.
    Guo, J., Jean, J., Nikolić, I., Qiao, K., Sasaki, Y., Sim, S.M.: Invariant subspace attack against full Midori64. Cryptology ePrint Archive, Report 2015/1189 (2015).
  26. 26.
    Kilian, J., Rogaway, P.: How to protect DES against exhaustive key search. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 252–267. Springer, Heidelberg (1996). doi: 10.1007/3-540-68697-5_20 Google Scholar
  27. 27.
    Knezevic, M., Nikov, V., Rombouts, P.: Low-latency encryption - Is “Lightweight = Light + Wait”? In: Prouff, E., Schaumont, P. (eds.) CHES 2012. LNCS, vol. 7428, pp. 426–446. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  28. 28.
    Knudsen, L., Leander, G., Poschmann, A., Robshaw, M.J.B.: PRINTcipher: a block cipher for ic-printing. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 16–32. Springer, Heidelberg (2010). doi: 10.1007/978-3-642-15031-9_2 CrossRefGoogle Scholar
  29. 29.
    Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999). doi: 10.1007/3-540-48405-1_25 CrossRefGoogle Scholar
  30. 30.
    Kulikowski, K.J., Su, M., Smirnov, A.B., Taubin, A., Karpovsky, M.G., MacDonald, D.: Delay insensitive encoding and power analysis: a balancing act. In: ASYNC, pp. 116–125. IEEE Computer Society (2005)Google Scholar
  31. 31.
    Liu, J., Yu, Y., Standaert, F.-X., Guo, Z., Gu, D., Sun, W., Ge, Y., Xie, X.: Small tweaks do not help: differential power analysis of MILENAGE implementations in 3G/4G USIM cards. In: Pernul, G., Ryan, P.Y.A., Weippl, E. (eds.) ESORICS 2015. LNCS, vol. 9326, pp. 468–480. Springer, Heidelberg (2015). doi: 10.1007/978-3-319-24174-6_24 CrossRefGoogle Scholar
  32. 32.
    Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, USA (2007)zbMATHGoogle Scholar
  33. 33.
    Moore, S.W., Mullins, R.D., Cunningham, P.A., Anderson, R.J., Taylor, G.S.: Improving smart card security using self-timed circuits. In: ASYNC, pp. 211–218. IEEE Computer Society (2002)Google Scholar
  34. 34.
    Moradi, A., Barenghi, A., Kasper, T., Paar, C.: On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs. In: ACM Conference on Computer and Communications Security - CCS 2011, pp. 111–124. ACM (2011)Google Scholar
  35. 35.
    Moradi, A., Immler, V.: Early propagation and imbalanced routing, how to diminish in FPGAs. In: Batina, L., Robshaw, M. (eds.) CHES 2014. LNCS, vol. 8731, pp. 598–615. Springer, Heidelberg (2014). doi: 10.1007/978-3-662-44709-3_33 Google Scholar
  36. 36.
    Moradi, A., Mischke, O., Paar, C.: Practical evaluation of DPA countermeasures on reconfigurable hardware. In: HOST 2011, pp. 154–160. IEEE (2011)Google Scholar
  37. 37.
    Moradi, A., Poschmann, A., Ling, S., Paar, C., Wang, H.: Pushing the limits: a very compact and a threshold implementation of AES. In: Paterson, K.G. (ed.) EUROCRYPT 2011. LNCS, vol. 6632, pp. 69–88. Springer, Heidelberg (2011). doi: 10.1007/978-3-642-20465-4_6 CrossRefGoogle Scholar
  38. 38.
    Moradi, A., Wild, A.: Assessment of hiding the higher-order leakages in hardware. In: Güneysu, T., Handschuh, H. (eds.) CHES 2015. LNCS, vol. 9293, pp. 453–474. Springer, Heidelberg (2015). doi: 10.1007/978-3-662-48324-4_23 CrossRefGoogle Scholar
  39. 39.
    Myers, C.J.: Asynchronous Circuit Design. Wiley, New York (2001)CrossRefGoogle Scholar
  40. 40.
    Nikova, S., Rijmen, V., Schläffer, M.: Secure hardware implementation of nonlinear functions in the presence of glitches. J. Cryptology 24(2), 292–321 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
  41. 41.
    Oswald, D., Paar, C.: Breaking mifare desfire MF3ICD40: power analysis and templates in the real world. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 207–222. Springer, Heidelberg (2011). doi: 10.1007/978-3-642-23951-9_14 CrossRefGoogle Scholar
  42. 42.
    Poschmann, A., Moradi, A., Khoo, K., Lim, C., Wang, H., Ling, S.: Side-channel resistant crypto for less than 2, 300 GE. J. Cryptology 24(2), 322–345 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
  43. 43.
    Poschmann, A.Y.: Lightweight cryptography: cryptographic engineering for a pervasive world. Ph.D. thesis, Ruhr University Bochum (2009)Google Scholar
  44. 44.
    Schneider, T., Moradi, A.: Leakage assessment methodology — a clear roadmap for side-channel evaluations. In: Güneysu, T., Handschuh, H. (eds.) CHES 2015. LNCS, vol. 9293, pp. 495–513. Springer, Heidelberg (2015). doi: 10.1007/978-3-662-48324-4_25 CrossRefGoogle Scholar
  45. 45.
    Spars, J., Furber, S.: Principles of Asynchronous Circuit Design: A Systems Perspective, 1st edn. Springer Publishing Company, Incorporated, USA (2010)Google Scholar
  46. 46.
    Standaert, F.-X., Örs, S.B., Preneel, B.: Power analysis of an FPGA: implementation of rijndael: is pipelining a DPA countermeasure? In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 30–44. Springer, Heidelberg (2004). doi: 10.1007/978-3-540-28632-5_3 CrossRefGoogle Scholar
  47. 47.
    Suzuki, D., Saeki, M.: Security evaluation of DPA countermeasures using dual-rail pre-charge logic style. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 255–269. Springer, Heidelberg (2006). doi: 10.1007/11894063_21 CrossRefGoogle Scholar
  48. 48.
    Tiri, K., Verbauwhede, I.: A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: Design, Automation and Test in Europe - DATE 2004, pp. 246–251. IEEE Computer Society (2004)Google Scholar
  49. 49.
    Virtual Silicon Inc.: 0.18 \(\upmu \)m VIP standard cell library tape out ready, Part number: UMCL18G212T3, Process: UMC Logic 0.18 \(\upmu \)m Generic II Technology: 0.18 \(\upmu \)m, July 2004Google Scholar
  50. 50.
    Wu, J., Kim, Y., Choi, M.: Low-power side-channel attack-resistant asynchronous s-box design for AES cryptosystems. In: ACM Great Lakes Symposium on VLSI, pp. 459–464. ACM (2010)Google Scholar
  51. 51.
    Yli-Mäyry, V., Homma, N., Aoki, T.: Improved power analysis on unrolled architecture and its application to PRINCE block cipher. In: Güneysu, T., Leander, G., Moradi, A. (eds.) LightSec 2015. LNCS, vol. 9542, pp. 148–163. Springer, Heidelberg (2016). doi: 10.1007/978-3-319-29078-2_9 CrossRefGoogle Scholar
  52. 52.
    Yu, A., Brée, D.S.: A clock-less implementation of the AES resists to power and timing attacks. In: ITCC (2), pp. 525–532. IEEE Computer Society (2004)Google Scholar
  53. 53.
    Yu, Z.C., Furber, S.B., Plana, L.A.: An investigation into the security of self-timed circuits. In: ASYNC, pp. 206–215. IEEE Computer Society (2003)Google Scholar
  54. 54.
    Zhou, Y., Yu, Y., Standaert, F.-X., Quisquater, J.-J.: On the need of physical security for small embedded devices: a case study with COMP128-1 implementations in SIM cards. In: Sadeghi, A.-R. (ed.) FC 2013. LNCS, vol. 7859, pp. 230–238. Springer, Heidelberg (2013). doi: 10.1007/978-3-642-39884-1_20 CrossRefGoogle Scholar

Copyright information

© International Association for Cryptologic Research 2016

Authors and Affiliations

  1. 1.Horst Görtz Institute for IT-SecurityRuhr-Universität BochumBochumGermany

Personalised recommendations