Advertisement

Mitigating SAT Attack on Logic Locking

  • Yang XieEmail author
  • Ankur Srivastava
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9813)

Abstract

Logic locking is a technique that has been proposed to protect outsourced IC designs from piracy and counterfeiting by untrusted foundries. A locked IC preserves the correct functionality only when a correct key is provided. Recently, the security of logic locking is threatened by a new attack called SAT attack, which can decipher the correct key of most logic locking techniques within a few hours [12] even for a reasonably large number of keys. This attack iteratively solves SAT formulas which progressively eliminate the incorrect keys till the circuit unlocked. In this paper, we present a circuit block (referred to as Anti-SAT block) to thwart the SAT attack. We show that the number of SAT attack iterations to reveal the correct key in a circuit comprising an Anti-SAT block is an exponential function of the key-size thereby making the SAT attack computationally infeasible. Through our experiments, we illustrate the effectiveness of our approach to securing modern chips fabricated in untrusted foundries.

Keywords

Logic locking SAT attack Hardware IP protection 

Notes

Acknowledgments

This work was supported by NSF under Grant No. 1223233 and AFOSR under Grant FA9550-14-1-0351.

References

  1. 1.
    Baumgarten, A., Tyagi, A., Zambreno, J.: Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)CrossRefGoogle Scholar
  2. 2.
    Dupuis, S., Ba, P.S., Di Natale, G., Flottes, M.L., Rouzeyre, B.: A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), pp. 49–54. IEEE (2014)Google Scholar
  3. 3.
    Guin, U., Huang, K., DiMase, D., Carulli, J.M., Tehranipoor, M., Makris, Y.: Counterfeit integrated circuits: a rising threat in the global semiconductor supply chain. Proc. IEEE 102(8), 1207–1228 (2014)CrossRefGoogle Scholar
  4. 4.
    HelionTechnology: High performance AES (Rijndael) cores for ASIC (2015). http://www.heliontech.com/downloads/aes_asic_helioncore.pdf
  5. 5.
    Khaleghi, S., Da Zhao, K., Rao, W.: IC piracy prevention via design withholding and entanglement. In: 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 821–826. IEEE (2015)Google Scholar
  6. 6.
    Liu, B., Wang, B.: Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks. In: Proceedings of the Conference on Design, Automation and Test in Europe, p. 243. European Design and Automation Association (2014)Google Scholar
  7. 7.
    Plaza, S.M., Markov, I.L.: Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 34(6), 961–971 (2015)CrossRefGoogle Scholar
  8. 8.
    Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Security analysis of logic obfuscation. In: Proceedings of the 49th Annual Design Automation Conference, pp. 83–89. ACM (2012)Google Scholar
  9. 9.
    Rajendran, J., Zhang, H., Zhang, C., Rose, G.S., Pino, Y., Sinanoglu, O., Karri, R.: Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410–424 (2015)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Rostami, M., Koushanfar, F., Karri, R.: A primer on hardware security: models, methods, and metrics. Proc. IEEE 102(8), 1283–1295 (2014)CrossRefGoogle Scholar
  11. 11.
    Roy, J.A., Koushanfar, F., Markov, I.L.: Epic: Ending piracy of integrated circuits. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1069–1074. ACM (2008)Google Scholar
  12. 12.
    Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143. IEEE (2015)Google Scholar
  13. 13.
    Wendt, J.B., Potkonjak, M.: Hardware obfuscation using PUF-based logic. In: Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, pp. 270–277. IEEE Press (2014)Google Scholar
  14. 14.
    Yasin, M., Rajendran, J., Sinanoglu, O., Karri, R.: On improving the security of logic locking. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. PP(99), 1 (2015)Google Scholar

Copyright information

© International Association for Cryptologic Research 2016

Authors and Affiliations

  1. 1.University of MarylandCollege ParkUSA

Personalised recommendations