Logic for Programming, Artificial Intelligence, and Reasoning

Logic for Programming, Artificial Intelligence, and Reasoning pp 340-355 | Cite as

Fine Grained SMT Proofs for the Theory of Fixed-Width Bit-Vectors

  • Liana Hadarean
  • Clark Barrett
  • Andrew Reynolds
  • Cesare Tinelli
  • Morgan Deters
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9450)

Abstract

Many high-level verification tools rely on SMT solvers to efficiently discharge complex verification conditions. Some applications require more than just a yes/no answer from the solver. For satisfiable quantifier-free problems, a satisfying assignment is a natural artifact. In the unsatisfiable case, an externally checkable proof can serve as a certificate of correctness and can be mined to gain additional insight into the problem. We present a method of encoding and checking SMT-generated proofs for the quantifier-free theory of fixed-width bit-vectors. Proof generation and checking for this theory poses several challenges, especially for proofs based on reductions to propositional logic. Such reductions can result in large resolution subproofs in addition to requiring a proof that the reduction itself is correct. We describe a fine-grained proof system formalized in the LFSC framework that addresses some of these challenges with the use of computational side-conditions. We report results using a proof-producing version of the CVC4 SMT solver on unsatisfiable quantifier-free bit-vector benchmarks from the SMT-LIB benchmark library.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Liana Hadarean
    • 1
  • Clark Barrett
    • 2
  • Andrew Reynolds
    • 3
  • Cesare Tinelli
    • 4
  • Morgan Deters
    • 2
  1. 1.Oxford UniversityOxfordEngland
  2. 2.New York UniversityNew YorkUSA
  3. 3.EPFLLausanneSwitzerland
  4. 4.The University of IowaIowa CityUSA

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