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Inherent Limitations of Hybrid Transactional Memory

  • Dan Alistarh
  • Justin Kopinsky
  • Petr Kuznetsov
  • Srivatsan RaviEmail author
  • Nir Shavit
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9363)

Abstract

Several Hybrid Transactional Memory (HyTM) schemes have recently been proposed to complement the fast, but best-effort nature of Hardware Transactional Memory (HTM) with a slow, reliable software backup. However, the costs of providing concurrency between hardware and software transactions in HyTM are still not well understood.

In this paper, we propose a general model for HyTM implementations, which captures the ability of hardware transactions to buffer memory accesses. The model allows us to formally quantify and analyze the amount of overhead (instrumentation) caused by the potential presence of software transactions. We prove that (1) it is impossible to build a strictly serializable HyTM implementation that has both uninstrumented reads and writes, even for very weak progress guarantees, and (2) the instrumentation cost incurred by a hardware transaction in any progressive opaque HyTM is linear in the size of the transaction’s data set. We further describe two implementations which exhibit optimal instrumentation costs for two different progress conditions. In sum, this paper proposes the first formal HyTM model and captures for the first time the trade-off between the degree of hardware-software TM concurrency and the amount of instrumentation overhead.

Keywords

Base Object Transactional Memory Software Transaction Cache Access Software Transactional Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Advanced Synchronization Facility Proposed Architectural Specification, March 2009. http://developer.amd.com/wordpress/media/2013/09/45432-ASF_Spec_2.1.pdf
  2. 2.
    Afek, Y., Levy, A., Morrison, A.: Software-improved hardware lock elision. In: PODC. ACM (2014)Google Scholar
  3. 3.
    Alistarh, D., Eugster, P., Herlihy, M., Matveev, A., Shavit, N.: Stacktrack: an automated transactional approach to concurrent memory reclamation. In: Proceedings of the Ninth European Conference on Computer Systems. EuroSys 2014, pp. 25:1–25:14. ACM, New York (2014)Google Scholar
  4. 4.
    Alistarh, D., Kopinsky, J., Kuznetsov, P., Ravi, S., Shavit, N.: Inherent limitations of hybrid transactional memory (2014). CoRR, abs/1405.5689. http://arxiv.org/abs/1405.5689
  5. 5.
    Ananian, C.S., Asanovic, K., Kuszmaul, B.C., Leiserson, C.E., Lie, S.: Unbounded transactional memory. In: Proceedings of the 11th International Symposium on High-Performance Computer Architecture. HPCA 2005, pp. 316–327. IEEE Computer Society, Washington (2005)Google Scholar
  6. 6.
    Attiya, H., Hillel, E.: The cost of privatization in software transactional memory. IEEE Trans. Computers 62(12), 2531–2543 (2013)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Attiya, H., Hillel, E., Milani, A.: Inherent limitations on disjoint-access parallel implementations of transactional memory. Theory of Computing Systems 49(4), 698–719 (2011)zbMATHMathSciNetCrossRefGoogle Scholar
  8. 8.
    Calciu, I., Shpeisman, T., Pokam, G., Herlihy, M.: Improved single global lock fallback for best-effort hardware transactional memory. In: Transact 2014 Workshop. ACM (2014)Google Scholar
  9. 9.
    Dalessandro, L., Carouge, F., White, S., Lev, Y., Moir, M., Scott, M.L., Spear, M.F.: Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory. In: Gupta, R., Mowry, T.C. (eds.) ASPLOS, pp. 39–52. ACM (2011)Google Scholar
  10. 10.
    Damron, P., Fedorova, A., Lev, Y., Luchangco, V., Moir, M., Nussbaum, D.: Hybrid transactional memory. SIGPLAN Not. 41(11), 336–346 (2006)CrossRefGoogle Scholar
  11. 11.
    Dice, D., Lev, Y., Moir, M., Nussbaum, D.: Early experience with a commercial hardware transactional memory implementation. In: Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems. ASPLOS XIV, pp. 157–168. ACM, New York (2009)Google Scholar
  12. 12.
    Dragojević, A., Herlihy, M., Lev, Y., Moir, M.: On the power of hardware transactional memory to simplify memory management. In: Proceedings of the 30th Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing. PODC 2011, pp. 99–108. ACM, New York (2011)Google Scholar
  13. 13.
    Guerraoui, R., Kapalka, M.: On obstruction-free transactions. In: Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures. SPAA 2008, pp. 304–313. ACM, New York (2008)Google Scholar
  14. 14.
    Guerraoui, R., Kapalka, M.: Principles of Transactional Memory. Synthesis Lectures on Distributed Computing Theory. Morgan and Claypool (2010)Google Scholar
  15. 15.
    Harris, T., Larus, J.R., Rajwar, R.: Transactional Memory, 2nd edn. Synthesis Lectures on Computer Architecture. Morgan & Claypool Publishers (2010)Google Scholar
  16. 16.
    Herlihy, M., Luchangco, V., Moir, M., Scherer III, W.N.: Software transactional memory for dynamic-sized data structures. In: Proceedings of the Twenty-Second Annual Symposium on Principles of Distributed Computing. PODC 2003, pp. 92–101. ACM, New York (2003)Google Scholar
  17. 17.
    Herlihy, M., Moss, J.E.B.: Transactional memory: architectural support for lock-free data structures. In: ISCA, pp. 289–300 (1993)Google Scholar
  18. 18.
    Kumar, S., Chu, M., Hughes, C.J., Kundu, P., Nguyen, A.: Hybrid transactional memory. In: Proceedings of the Eleventh ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. PPoPP 2006, pp. 209–220. ACM, New York (2006)Google Scholar
  19. 19.
    Lev, Y., Moir, M., Nussbaum, D.: Phtm: phased transactional memory. In: Workshop on Transactional Computing (Transact) (2007). http://research.sun.com/scalable/pubs/TRANSACT2007PhTM.pdf
  20. 20.
    Matveev, A., Shavit, N.: Reduced hardware transactions: a new approach to hybrid transactional memory. In: Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, pp. 11–22. ACM (2013)Google Scholar
  21. 21.
    Ohmacht, M.: Memory Speculation of the Blue Gene/Q Compute Chip (2011). http://wands.cse.lehigh.edu/IBM_BQC_PACT2011.ppt
  22. 22.
  23. 23.
  24. 24.
    Riegel, T., Marlier, P., Nowack, M., Felber, P., Fetzer, C.: Optimizing hybrid transactional memory: the importance of nonspeculative operations. In: Proceedings of the 23rd ACM Symposium on Parallelism in Algorithms and Architectures, pp. 53–64. ACM (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Dan Alistarh
    • 1
  • Justin Kopinsky
    • 2
  • Petr Kuznetsov
    • 3
  • Srivatsan Ravi
    • 4
    Email author
  • Nir Shavit
    • 2
    • 5
  1. 1.Microsoft ResearchCambridgeUK
  2. 2.Massachuseets University of TechnologyCambridgeUSA
  3. 3.Télécom ParisTechParisFrance
  4. 4.TU BerlinBerlinGermany
  5. 5.Tel Aviv UniversityTel AvivIsrael

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