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Accelerating Homomorphic Evaluation on Reconfigurable Hardware

  • Thomas Pöppelmann
  • Michael Naehrig
  • Andrew Putnam
  • Adrian Macias
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9293)

Abstract

Homomorphic encryption allows computation on encrypted data and makes it possible to securely outsource computational tasks to untrusted environments. However, all proposed schemes are quite inefficient and homomorphic evaluation of ciphertexts usually takes several seconds on high-end CPUs, even for evaluating simple functions. In this work we investigate the potential of FPGAs for speeding up those evaluation operations. We propose an architecture to accelerate schemes based on the ring learning with errors (RLWE) problem and specifically implemented the somewhat homomorphic encryption scheme YASHE, which was proposed by Bos, Lauter, Loftus, and Naehrig in 2013. Due to the large size of ciphertexts and evaluation keys, on-chip storage of all data is not possible and external memory is required. For efficient utilization of the external memory we propose an efficient double-buffered memory access scheme and a polynomial multiplier based on the number theoretic transform (NTT). For the parameter set (\(n=16384,\lceil \log _2 q \rceil ={512}\)) capable of evaluating 9 levels of multiplications, we can perform a homomorphic addition in 0.94 ms and a homomorphic multiplication in 48.67 ms.

Keywords

Homomorphic encryption Ring learning with errors FPGA Reconfigurable computing 

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Copyright information

© International Association for Cryptologic Research 2015

Authors and Affiliations

  • Thomas Pöppelmann
    • 1
  • Michael Naehrig
    • 2
  • Andrew Putnam
    • 2
  • Adrian Macias
    • 3
  1. 1.Horst Görtz Institute for IT-SecurityRuhr-University BochumBochumGermany
  2. 2.Microsoft ResearchRedmondUSA
  3. 3.Altera CorporationSan DiegoUSA

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