Effective Barrier Synchronization on Intel Xeon Phi Coprocessor

  • Andrey Rodchenko
  • Andy Nisbet
  • Antoniu Pop
  • Mikel Luján
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9233)

Abstract

Barriers are a fundamental synchronization primitive, underpinning the parallel execution models of many modern shared-memory parallel programming languages such as OpenMP, OpenCL or Cilk, and are one of the main challenges to scaling. State-of-the-art barrier synchronization algorithms differ in tradeoffs between critical path length, communication traffic patterns and memory footprint. In this paper, we evaluate the efficiency of five such algorithms on the Intel Xeon Phi coprocessor. In addition, we present a novel hybrid barrier implementation that exploits the topology, the memory hierarchy and streaming stores of the Xeon Phi architecture to achieve a 3\(\times \) lower overhead than the Intel OpenMP barrier implementation (ICC 14.0.0), thus outperforming, to the best of our knowledge, all other implementations, and which we evaluate on the CG and MG kernels from the NAS Parallel Benchmarks, the direct N-body simulation kernel and the EPCC barrier OpenMP microbenchmark. The optimized barriers presented in the paper are available at https://github.com/arodchen/cbarriers released as free software.

Keywords

Barrier synchronization Scalability Algorithms Many-core architectures Intel Xeon Phi 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Andrey Rodchenko
    • 1
  • Andy Nisbet
    • 1
  • Antoniu Pop
    • 1
  • Mikel Luján
    • 1
  1. 1.School of Computer ScienceThe University of ManchesterManchesterUK

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