Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip

  • Abderahman Kriouile
  • Wendelin Serwe
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9035)


In this paper we report about a case study on the functional verification of a System-on-Chip (SoC) with a formal system-level model. Our approach improves industrial simulation-based verification techniques in two aspects. First, we suggest to use the formal model to assess the sanity of an interface verification unit. Second, we present a two-step approach to generate clever semi-directed test cases from temporal logic properties: model-based testing tools of the CADP toolbox generate system-level abstract test cases, which are then refined with a commercial Coverage-Directed Test Generation tool into interface-level concrete test cases that can be executed at RTL level. Applied to an AMBA 4 ACE-based cache-coherent SoC, we found that our approach helps in the transition from interface-level to system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench.


Model Check Test Generation Label Transition System Cache Line Address Read 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Abderahman Kriouile
    • 1
    • 2
    • 3
    • 4
  • Wendelin Serwe
    • 2
    • 3
    • 4
  1. 1.STMicroelectronicsGrenobleFrance
  2. 2.InriaGrenobleFrance
  3. 3.Univ. Grenoble Alpes, LIGGrenobleFrance
  4. 4.CNRS, LIGGrenobleFrance

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