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Path Sensitive Cache Analysis Using Cache Miss Paths

  • Kartik Nagar
  • Y. N. Srikant
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8931)

Abstract

Cache analysis plays a very important role in obtaining precise Worst Case Execution Time (WCET) estimates of programs for real-time systems. While Abstract Interpretation based approaches are almost universally used for cache analysis, they fail to take advantage of its unique requirement: it is not necessary to find the guaranteed cache behavior that holds across all executions of a program. We only need the cache behavior along one particular program path, which is the path with the maximum execution time. In this work, we introduce the concept of cache miss paths, which allows us to use the worst-case path information to improve the precision of AI-based cache analysis. We use Abstract Interpretation to determine the cache miss paths, and then integrate them in the IPET formulation. An added advantage is that this further allows us to use infeasible path information for cache analysis. Experimentally, our approach gives more precise WCETs as compared to AI-based cache analysis, and we also provide techniques to trade-off analysis time with precision to provide scalability.

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References

  1. 1.
    Ferdinand, C., Wilhelm, R.: Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems 17(2-3), 131–181 (1999)Google Scholar
  2. 2.
    Li, Y.T.-S., Malik, S., Wolfe, A.: Efficient microarchitecture modeling and path analysis for real-time software. In: 16th IEEE Real-Time Systems Symposium, pp. 298–307 (1995)Google Scholar
  3. 3.
    Gustafsson, J., Ermedahl, A., Sandberg, C., Lisper, B.: Automatic Derivation of Loop Bounds and Infeasible Paths for WCET Analysis Using Abstract Execution. In: 27th IEEE Real-Time Systems Symposium, pp. 57–66 (December 2006)Google Scholar
  4. 4.
    Engblom, J., Ermedahl, A.: Modeling complex flows for worst-case execution time analysis. In: 21st IEEE Real-Time Systems Symposium, pp. 163–174 (2000)Google Scholar
  5. 5.
    Blackham, B., Liffiton, M., Heiser, G.: Trickle:automated infeasible path detection using all minimal unsatisfiable subsets. In: 20th IEEE Real-time and Embedded Technology and Applications Symposium (2014)Google Scholar
  6. 6.
    Nagar, K., Srikant, Y.N.: Precise shared cache analysis using optimal interference placement. In: 20th IEEE Real-time and Embedded Technology and Applications Symposium (2014)Google Scholar
  7. 7.
    Chattopadhyay, S., Roychoudhury, A.: Scalable and Precise Refinement of Cache Timing Analysis via Model Checking. In: 32nd IEEE Real-Time Systems Symposium, pp. 193–203 (2011)Google Scholar
  8. 8.
    Banerjee, A., Chattopadhyay, S., Roychoudhury, A.: Precise micro-architectural modeling for WCET analysis via AI+SAT. In: 19th IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 87–96 (2013)Google Scholar
  9. 9.
    Li, Y.T.-S., Malik, S., Wolfe, A.: Cache modeling for real-time software: beyond direct mapped instruction caches. In: 17th IEEE Real-Time Systems Symposium, pp. 254–263 (1996)Google Scholar
  10. 10.
    Wilhelm, R.: Why AI + ILP Is Good for WCET, but MC Is Not, Nor ILP Alone. In: Steffen, B., Levi, G. (eds.) VMCAI 2004. LNCS, vol. 2937, pp. 309–322. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  11. 11.
    Huynh, B.K., Ju, L.: Roychoudhury, A.: Scope-Aware Data Cache Analysis for WCET Estimation. In: 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 203–212 (2011)Google Scholar
  12. 12.
    Clarke, R., Grumberg, O., Jha, S., Lu, Y., Veith, H.: Counterexample-guided abstraction refinement for symbolic model checking. J. ACM 50(5), 752–794 (2003)CrossRefMathSciNetGoogle Scholar
  13. 13.
    Cerny, P., Henzinger, T., Radhakrishna, A.: Quantitative abstraction refinement. In: Proceedings of the 40th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL), pp. 115–128 (2013)Google Scholar
  14. 14.
    Li, X., Liang, Y., Mitra, T., Roychoudhury, A.: Chronos: A Timing Analyzer for Embedded Software. Science of Computer Programming 69(1-3), 56–67 (2007)CrossRefzbMATHMathSciNetGoogle Scholar
  15. 15.

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Kartik Nagar
    • 1
  • Y. N. Srikant
    • 1
  1. 1.Indian Institute of ScienceBangaloreIndia

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