Automated Framework for General-Purpose Genetic Algorithms in FPGAs

  • Liucheng GuoEmail author
  • David B. Thomas
  • Wayne Luk
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8602)


FPGA-based Genetic Algorithms (GAs) have been effective for optimisation of many real-world applications, but require extensive customisation of the hardware GA architecture. To promote these accelerated GAs to potential users without hardware design experience, this paper proposes an automated framework for creating and executing general-purpose GAs in FPGAs. The framework contains a scalable and customisable hardware architecture, which provides a unified platform for both binary and real-valued chromosomes. At compile-time, a user only needs to provide a high-level specification of the target application, without writing any hardware-specific code in low-level languages such as VHDL or Verilog. At run-time, a user can tune application inputs and GA parameters without time-consuming recompilation, in order to find a good configuration for further GA executions. The framework is demonstrated on a high performance FPGA platform to solve six problems and benchmarks, including a locating problem and the NP-hard set covering problem. Experiments show our custom GA is more flexible and easier to use compared to existing FPGA-based GAs, and achieves an average speed-up of 30 times compared to a multi-core CPU.


Genetic Algorithm FPGA Automated Framework 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Shackleford, B., Snider, G., Carter, R.: A high-performance, pipelined, FPGA-based genetic algorithm machine. Genetic Programming and Evolvable Machines 2(1), 33–60 (2001)CrossRefzbMATHGoogle Scholar
  2. 2.
    Aporntewan, C., Chongstilivatana, P.: A hardware implementation of the compact genetic algorithm. In: Proceedings of the 2001 Congress on Evolutionary Computation, vol. 1, pp. 624–629 (2001)Google Scholar
  3. 3.
    Plessl, C., Platzner, M.: Custom computing machines for the set covering problem. In: Proceedings of 10th IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 163–172 (2002)Google Scholar
  4. 4.
    Coley, D.A.: An introduction to genetic algorithms for scientists and engineers. World Scientific Publishing, Singapore (2003)Google Scholar
  5. 5.
    Balas, E.: A class of location, distribution and scheduling problems: Modeling and solution methods (1982)Google Scholar
  6. 6.
    Guo, L., Thomas, D., Luk, W.: Customisable architectures for the set covering problem. In: Proceedings of International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), pp. 69–74 (June 2013)Google Scholar
  7. 7.
    Maxeler Tech, Programming MPC Systems White Paper (2013)Google Scholar
  8. 8.
    Vavouas, M., Papadimitriou, K., Papaefstathiou, I.: High-speed FPGA-based implementations of a genetic algorithm. In: Systems, Architectures, Modeling, and Simulation, pp. 9–16 (2009)Google Scholar
  9. 9.
    Yoshida, N., Yasuoka, T.: Multi-GAP: parallel and distributed genetic algorithms in VLSI. In: Proceedings of IEEE International Conference on Systems, Man, and Cybernetics, vol. 5, pp. 571–576 (1999)Google Scholar
  10. 10.
    Fernando, P., Katkoori, S.: Customisable FPGA IP core implementation of a general-purpose genetic algorithm engine. IEEE Transactions on Evolutionary Computation 14(1), 133–149 (2010)CrossRefGoogle Scholar
  11. 11.
    Ecuyer, P.L.: Tables of maximally equidistributed combined LFSR generators. Mathematics of computation 68(225), 261–269 (1999)CrossRefzbMATHMathSciNetGoogle Scholar
  12. 12.
    Haupt, R.L., Haupt, S.E.: Practical genetic algorithms. John Wiley & Sons (2004)Google Scholar
  13. 13.
    Scott, S., Samal, A., Seth, S.: HGA: A hardware-based genetic algorithm. In: ACM 3rd International Symposium on Field-Programmable Gate Arrays, pp. 53–59 (1995)Google Scholar
  14. 14.
    Sivanandam, S.N., Deepa, S.N.: Introduction to genetic algorithms. Springer (2007)Google Scholar
  15. 15.
    Tang, W., Yip, L.: Hardware implementation of genetic algorithms using FPGA. In: 47th IEEE Midwest Symposium on Circuits and Systems, pp. 549–552 (2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  1. 1.Department of EEEImperial College LondonLondonUK
  2. 2.Department of ComputingImperial College LondonLondonUK

Personalised recommendations