Advanced Computer Architecture pp 177-189 | Cite as
Dynamic Power Estimation with Hardware Performance Counters Support on Multi-core Platform
Conference paper
Abstract
Power estimation has attracted a plenty of attentions for its significant guidance for OS scheduling and the development of power-efficiency optimization design. Previous researches indicate that power consumption can be estimated via monitoring related hardware events, such as retirement of instructions, cache access, etc. However, these models based on hardware events will introduce an error around 5%. In this paper, a more accurate hardware events directed power model is proposed. We identified the most appropriate events to respond to the major power consumption components. By analyzing the hardware events in processor through performance counters, a unified run-time power estimation model is introduced. Our model has been verified through real-time measurement and shown to be 3.01% and 1.99% inaccurate for PARSEC and SPLASH-2 benchmark suites. Our power estimation model can serve as a foundation for intelligent, power-aware systems that can dynamically balance power assignment and smooth peak power at run-time.
Keywords
Dynamic Power Power Estimation Performance CountersPreview
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