Analyzing and Simulating Time Descriptions from UML/MARTE CCSL

  • Judith Peters
  • Rolf Drechsler


The complexity of modern embedded systems makes it inevitable to consider higher abstraction levels in the design process to overcome problems in acceptable time and effort. In higher abstraction levels, the utilization of functional requirements is quite advanced, while the utilization of non-functional requirements like timing still is an open problem. We aim to address this problem utilizing the timing definitions from UML/MARTE CCSL.


CCSL, UML, MARTE, SystemC, Formal Methods 


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Copyright information

© Springer Fachmedien Wiesbaden 2015

Authors and Affiliations

  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany

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