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Analyzing and Simulating Time Descriptions from UML/MARTE CCSL

  • Judith Peters
  • Rolf Drechsler
Chapter

Abstract

The complexity of modern embedded systems makes it inevitable to consider higher abstraction levels in the design process to overcome problems in acceptable time and effort. In higher abstraction levels, the utilization of functional requirements is quite advanced, while the utilization of non-functional requirements like timing still is an open problem. We aim to address this problem utilizing the timing definitions from UML/MARTE CCSL.

Keywords:

CCSL, UML, MARTE, SystemC, Formal Methods 

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References

  1. 1.
    Object Management Group: UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems. Object Management Group (2011)Google Scholar
  2. 2.
    Object Management Group: OMG Unified Modeling Language TM (OMG UML) Superstructure. Object Management Group (2011)Google Scholar
  3. 3.
    Peters, J., Wille, R., Drechsler, R.: Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL. International Conference on Engineering of Complex Computer Systems (ICECCS), 116-125 (2014)Google Scholar
  4. 4.
    Drechsler, R., Soeken, M., Wille, R.: Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing. Forum on Specification and Design Languages (FDL), 53-58 (2012)Google Scholar
  5. 5.
    Mallet, F., Yin, L.: Correct Transformation from CCSL to Promela for verification. Institut National de Recherche en Informatique et en Automatique, (2012)Google Scholar

Copyright information

© Springer Fachmedien Wiesbaden 2015

Authors and Affiliations

  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany

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