HIPARE: Hierarchical Circuit and Parameter Extraction from Mask Layout Data

  • U. Röttcher
  • J. Fritz
  • F. Krohm
  • G. Hess
Conference paper
Part of the Informatik—Fachberichte book series (INFORMATIK, volume 255)

Abstract

HIPARE performs hierarchical circuit and parameter extraction from mask layout data including non-Manhattan geometries. Due to its programming modularity and a powerful set of layout operations HIPARE is very flexible in adapting to different technologies and can compute almost all usual device types and their parameters. Additionally, sophisticated algorithms for detailed parasitics such as resistances, intrinsic and intemodal capacitances of arbitrary conductors have been implemented. Hierarchical analysis is based on user-defined abstract representations of cells allowing overlaps and inner-cell interfaces.

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References

  1. /1/.
    S.P. McCormick, “EXCL: A Circuit Extractor for IC Designs,” Proc. 21st Design Automation Conference, pp. 616–623, Jun. 1984.Google Scholar
  2. /2/.
    W.S. Scott, J.K. Ousterhout, “Magic’s Circuit Extractor,” Proc. 22nd Design Automation Conference, pp. 286–292, Jun. 1985.Google Scholar
  3. /3/.
    V. Henkel, U.Golze, “RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification Based on Interaction Rules,” Proc. Conf. CICC, 1988.Google Scholar
  4. /4/.
    Y. Wong, “Hierarchical Circuit Verification,” Proc. 22nd Design Automation Conf, pp. 695–701, 1985.Google Scholar
  5. /5/.
    T.J. Wagner, “Hierarchical Layout Verification,” Proc. 21st Design Automation Conf, pp. 484–489, 1984.Google Scholar
  6. /6/.
    G.M. Tarolli, W.J. Herman, “Hierachical Circuit Extraction with Detailed Parasitic Capacitance,” Proc. 20th Design Automation Conf, pp. 337–345, 1983.Google Scholar
  7. /7/.
    S.C. Johnson, “Hierarchical Design Validation Based on Rectangles,” Proc. Conf. on Advanced Research in VLSI, pp. 97–100, 1982.Google Scholar
  8. /8/.
    A. Bootehsaz, R.A. Courel, “A Technology Independent Approach to Hierarchical IC Layout Extraction,” Proc. 23rd Design Automation Conf, pp. 425–431, 1986.Google Scholar
  9. /9/.
    L.K. Scheffer, R. Soetarman, “Hierarchical Analysis of IC Artwork with User-Defined Rules,” IEEE Design & Test, pp. 66–74, 1986.Google Scholar
  10. /10/.
    U. Lauther, “An O(N log N) Algorithm fcr Boolean Mask Operations,” Proc. 18th Design Automation Conference, pp. 555–562, Jun. 1981.Google Scholar
  11. /11/.
    J.L. Bentley, T.A. Ottmann, “Algorithms for Reporting and Counting Geometric Intersections,” IEEE Transactions on Computers, VOL. C-28, NO. 9, pp. 643–647, Sept. 1979.CrossRefGoogle Scholar
  12. /12/.
    T. Sakurai, K. Tamaru, “Simple Formulas for Two-and Three-Dimensional Capacitances,” IEEE Trans. on Electron Devices, Vol. ED-30, No. 2, pp. 183–185, 1983.CrossRefGoogle Scholar
  13. /13/.
    M. Horowitz, R.W. Dutton, “Resistance Extraction from Mask Layout Data”, IEEE Trans. on CAD, Vol. CAD-2, No. 3, pp. 478–481, 1979.Google Scholar
  14. /14/.
    J. Bentley, T. Ottmann, “The Complexity of Manipulating Hierarchically Defined Sets of Rectangles,” Technical Report, Carnegie Mellon University, 1981.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • U. Röttcher
    • 1
  • J. Fritz
    • 1
  • F. Krohm
    • 1
  • G. Hess
    • 1
  1. 1.Fraunhofer Institute of Microelectronic Circuits and SystemsDuisburg 1Germany

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