Architektur von Rechensystemen pp 318-332 | Cite as
Developing a Processing Node Architecture for a Parallel Computer
Abstract
A massively parallel computer with distributed memory for database, Lisp and Prolog is currently being developed. It provides two different communication mechanisms: explicit message passing and a virtually shared memory. We identify the requirements the system imposes on the design of the single processing node. A node consists of processor(s), local memory, and a communication unit for the communication between the nodes. Possible node architectures are outlined and evaluated with respect to their performance in the parallel environment. We choose an architecture that does not only provide a processor for calculations, but additionally a second processor for communication support. Important criteria for the selection of a suitable processor are the cache coherency protocol and the control interface to the communication unit. We give reasons for our processor choice. Another focus of this paper is the communication unit that is being implemented as an ASIC. We describe the interaction between the different node components that allows fast internode communication.
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