Timing Analysis and Verification

Abstract

The new design methodology of the Capitol chip set generated new requirements for timing verification. The size of the design required to split the chips into several partitions, that were synthesized independent of each other using LSS. With the LSS internal delay calculator, timing requirements could be determined as long as the paths were totally within the partition. However the large chips include paths which spread over several partitions. Therefore an additional tool, the “Timing Analyzer”, was required, which could calculate timings for paths which spread over several partitions. The knowledge of the slack, defined as the difference of the actual and required arrival time of a net, will not be sufficient. This is because each partition should correct only a part of the overall slack, such that the total path delay meets the requirement.