MIPS: A VLSI Processor Architecture
MIPS (Microprocessor without Interlocked Pipe Stages) is a general purpose processor architecture designed to be implemented on a single VLSI chip. The main goal of the design is high performance in the execution of compiled code. The architecture is experimental since it is a radical break with the trend of modern computer architectures. The basic philosophy of MIPS is to present an instruction set that is a compiler-driven encoding of the microengine. Thus, little or no decoding is needed and the instructions correspond closely to microcode instructions. The processor is pipelined but provides no pipeline interlock hardware; this function must be provided by software.
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- 1.Baskett, F. Puzzle: an informal compute bound benchmark, widely circulated and runGoogle Scholar
- 2.Henncssy, J.L. SLIM: A Language for Simulation and PLA Generation in VLSI. Tech. Rept. 195, Computer Systems Laboratory, Stanford University, 1980.Google Scholar
- 3.Lampson, B.W., McDaniel, G.A. and S.M. Ornstein. An Instruction Fctch Unit for a High Performance Personal Computer. Tech. Rept. CSL-81-1, Xerox PARC, Jan, 1981Google Scholar
- 4.Patterson, D.A. and Sequin C.H. RISC-I: A Reduced Instruction Set VLSI Computer. Proc. of the Eighth Annual Symposium on Computer Architecture, Minneapolis, Minn., May, 1981.Google Scholar
- 5.Widdoes, L.C. The S-l Project: Developing high performance digital computers. Proc. Compcon, IEEE, San Francisco, Feb, 1980.Google Scholar