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A Wavefront Notation Tool for VLSI Array Design

  • Uri Weiser
  • Al Davis

Abstract

This paper presents an overview of an extension to a mathematically based methodology for mapping an algorithmic description into a concurrent implementation on silicon. The result of this methodology yields a systolic array [4]. The basic mathematical method was initially described by Cohen [1]. Extensions were made by Weiser and Davis [5]; Johnsson, Weiser, Cohen, and Davis [2]; Cohen and Johnsson [3]; and Weiser [6]. This approach focuses on the correspondence between equations defining a certain computation and networks which perform the computation. As the complexity of problems increases, a hierarchical approach can reduce the complexity by hiding detail and thus reduce the design complexity at each level. The purpose of this paper is to introduce a method for treating sets of data as wavefront entities in the equations of the mathematical methodology and in the graphical representation.

Keywords

Data Stream Discrete Fourier Transform Data Element Systolic Array Delay Operator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Cohen, D. Mathematical approach to iterative computation networks. Proceedings of the Fourth Symposium on Computer Arithmetic, October, 1978, pp. 226–238. Also ISI/RR-78-73, USC/Information Sciences Institute [4676 Admiralty Way, Marina del Rey, CA 90291], November 1978.Google Scholar
  2. 2.
    Johnsson, L. and Weiser, U. and Cohen, D. and Davis A. L. Towards a formal treatment of VLSI arrays. Procedings of the Caltech Conference on Very Large Scale Integration, January, 1981.Google Scholar
  3. 3.
    Johnsson L. and Cohen D. Comutational Array for the Discrete Fourier Transform. Compcon81, February, 1981, pp. 236–244.Google Scholar
  4. 4.
    Kung, H. T. and Leiserson, C. S. Systolic arrays (For VLSI). Tech. Rept. CMU-CS-79-103, Carnegie-Mellon University, 1978.Google Scholar
  5. 5.
    Weiser, U. and Davis, A. L. Mathematical representations for VLSI processor arrays. Tech. Rept. UUCS-80-111, University of Utah, September, 1980.Google Scholar
  6. 6.
    Weiser, U. Mathematical and Graphical Tools for the Creation of Computational Arrays. Ph.D. Th., University of Utah, July 1981. Dept. of Comput. Sci.Google Scholar

Copyright information

© Carnegie-Mellon University 1981

Authors and Affiliations

  • Uri Weiser
    • 1
  • Al Davis
    • 1
  1. 1.Computer Science DepartmentUniversity of UtahSalt Lake CityUSA

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