SAT-Based Synthesis Methods for Safety Specs

  • Roderick Bloem
  • Robert Könighofer
  • Martina Seidl
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8318)


Automatic synthesis of hardware components from declarative specifications is an ambitious endeavor in computer aided design. Existing synthesis algorithms are often implemented with Binary Decision Diagrams (BDDs), inheriting their scalability limitations. Instead of BDDs, we propose several new methods to synthesize finite-state systems from safety specifications using decision procedures for the satisfiability of quantified and unquantified Boolean formulas (SAT-, QBF- and EPR-solvers). The presented approaches are based on computational learning, templates, or reduction to first-order logic. We also present an efficient parallelization, and optimizations to utilize reachability information and incremental solving. Finally, we compare all methods in an extensive case study. Our new methods outperform BDDs and other existing work on some classes of benchmarks, and our parallelization achieves a super-linear speedup.


Reactive Synthesis SAT-Solving Quantified Boolean Formulas Effectively Propositional Logic 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  • Roderick Bloem
    • 1
  • Robert Könighofer
    • 1
  • Martina Seidl
    • 2
  1. 1.Institute for Applied Information Processing and Communications (IAIK)Graz University of TechnologyAustria
  2. 2.Institute for Formal Models and VerificationJohannes Kepler UniversityLinzAustria

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