A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks
- Cite this paper as:
- Xiao Z., Baas B. (2013) A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. In: Burg A., Coṣkun A., Guthaus M., Katkoori S., Reis R. (eds) VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. VLSI-SoC 2012. IFIP Advances in Information and Communication Technology, vol 418. Springer, Berlin, Heidelberg
Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective inter-processor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application inter-processor communication distance reduction of 19%.
KeywordsCMOS many-core processor interconnection topology network on chip (NoC) digital signal processing (DSP)
Unable to display preview. Download preview PDF.