Advertisement

Configurable Low-Latency Interconnect for Multi-core Clusters

  • Giulia Beanato
  • Igor Loi
  • Giovanni De Micheli
  • Yusuf Leblebici
  • Luca Benini
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 418)

Abstract

Shared L1 memories are of interest for tightly-coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest possible L1 working set. The advent of 3D technology provides new opportunities to improve the interconnect delay and the form factor. In this chapter we propose a network architecture, 3D-LIN, based on 3D integration technology. The network can be configured based on user specifications and technology constraints to provide fast access to L1 memories on multiple stacked dies. The extracted results from the physical synthesis of 3D-LIN permit to explore trade-offs between memory size and network latency from a planar design to multiple memory layers stacked on top of logic, evaluating the improvement in both form factor and latency.

Keywords

3D integration multi-core processor shared memory interconnection network 

References

  1. 1.
    Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W., Peh, L.-S.: Research challenges for on-chip interconnection networks. IEEE Micro 27, 96–108 (2007)Google Scholar
  2. 2.
    Borkar, S., Chien, A.A.: The Future of Microprocessors. Commun. ACM 54, 67–77 (2011)Google Scholar
  3. 3.
    Benini, L., De Micheli, G.: Networks on Chips: a New SoC Paradigm. Computer 35, 70–78 (2002)Google Scholar
  4. 4.
    Balkan, A., Qu, G., Vishkin, U.: A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing Application-Specific Systems. In: International Conference on Architectures and Processors, pp. 73–80 (2006)Google Scholar
  5. 5.
    Plurality, Ltd.: The hyperCore architecture. White Paper (2010)Google Scholar
  6. 6.
    Rahimi, A., Loi, I., Kakoee, M., Benini, L.: A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters Design. In: Automation Test in Europe Conference, pp. 1–6 (2011)Google Scholar
  7. 7.
    Xie, Y.: Processor Architecture Design Using 3D Integration Technology. In: 23rd International Conference on VLSI Design, pp. 446–451 (2010)Google Scholar
  8. 8.
    Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and management of 3D chip multiprocessors using network-in-memory. SIGARCH Comput. Archit. News 34, 130–141 (2006)Google Scholar
  9. 9.
    Loh, G.: 3D-Stacked memory architectures for multi-core processors. In: Proceedings of the 35th Annual International Symposium on Computer Architecture, pp. 453–464 (2008)Google Scholar
  10. 10.
    Woo, D.H., Seong, N.H., Lewis, D., Lee, H.-H.: An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth. In: 16th International Symposium on High Performance Computer Architecture, pp. 1–12 (2010)Google Scholar
  11. 11.
    Madan, N., Zhao, L., Muralimanohar, N., Udipi, A., Balasubramonian, R., Iyer, R., Makineni, S., Newell, D.: Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. In: 15th International Symposium on High Performance Computer Architecture, pp. 262–274 (2009)Google Scholar
  12. 12.
    Mishra, A., Dong, X., Sun, G., Xie, Y., Vijaykrishnan, N., Das, C.: Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. SIGARCH Comput. Archit. News 39, 69–80 (2011)Google Scholar
  13. 13.
    Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. SIGARCH Comput. Archit. News 34, 130–141 (2006)CrossRefzbMATHGoogle Scholar
  14. 14.
    Kim, J., Nicopoulos, C., Park, D., Das, R., Xie, Y., Narayanan, V., Yousif, M., Das, C.: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. In: 34th International Symposium on Computer Architecture, pp. 138–149 (2007)Google Scholar
  15. 15.
    Park, D., Eachempati, S., Das, R., Mishra, A., Xie, Y., Vijaykrishnan, N., Das, C.: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. In: 35th Annual International Symposium on Computer Architecture, pp. 251–261 (2008)Google Scholar
  16. 16.
    Xu, Y., Du, Y., Zhao, B., Zhou, X., Zhang, Y., Yang, J.: A Low-Radix and Low-Diameter 3D Interconnection Network Design. In: 15th International Symposium on High Performance Computer Architecture, pp. 30–42 (2009)Google Scholar
  17. 17.
    Xue, L., Gao, Y., Fu, J.: A High Performance 3D Interconnection Network for Many-Core Processors. In: 2nd International Conference on Computer Engineering and Technology, pp. 383–389 (2010)Google Scholar
  18. 18.
    Ben Ahmed, A., Ben Abdallah, A., Kuroda, K.: Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC. In: Broadband, Wireless Computing, Communication and Applications, pp. 67–73 (2010)Google Scholar
  19. 19.
    Design Compiler User Guide, Synopsys, version F-2011.09-SP2 (2011)Google Scholar
  20. 20.
    Van der Plas, G., Limaye, P., Loi, I., Mercha, A., Oprins, H., Torregiani, C., Thijs, S., Linten, D., Stucchi, M., Katti, G., Velenis, D., Cherman, V., Vandevelde, B., Simons, V., De Wolf, I., Labie, R., Perry, D., Bronckers, S., Minas, N., Cupac, M., Ruythooren, W., Van Olmen, J., Phommahaxay, A., de Potter de ten Broeck, M., Opdebeeck, A., Rakowski, M., De Wachter, B., Dehan, M., Nelis, M., Agarwal, R., Pullini, A., Angiolini, F., Benini, L., Dehaene, W., Travaly, Y., Beyne, E., Marchal, P.: Design issues and considerations for low-cost 3-D TSV IC technology. J. of Solid-State Circuits 46, 293–307 (2011)CrossRefGoogle Scholar
  21. 21.
    Kim, D.H., Mukhopadhyay, S., Lim, S.K.: Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling. IEEE Transactions on Components Packaging and Manufacturing Technology 1, 168–180 (2011)CrossRefGoogle Scholar
  22. 22.
    Shi, B., Srivastava, A.: Liquid Cooling for 3D-ICs. In: International Green Computing Conference and Workshops, July 25-28, pp. 1–6, (2011)Google Scholar
  23. 23.
    Zhou, X., Yang, J., Xu, Y., Zhang, Y., Zhao, J.: Thermal-aware Task Scheduling for 3D Multicore Processors. IEEE Trans. Parallel Distrib. Syst. 21, 60–71 (2010)CrossRefGoogle Scholar
  24. 24.
    Goplen, B., Sapatnekar, S.: Thermal Via Placement in 3D ICs. In: International Symposium on Physical Design, pp. 167–174 (2005)Google Scholar
  25. 25.
    Yu, H., He, L.: Dynamic Power and Thermal Integrity in 3D Integration. In: Communications, Circuits and Systems, pp. 1108–1112 (2009)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2013

Authors and Affiliations

  • Giulia Beanato
    • 1
  • Igor Loi
    • 2
  • Giovanni De Micheli
    • 1
  • Yusuf Leblebici
    • 1
  • Luca Benini
    • 2
  1. 1.EPFLLausanneSwitzerland
  2. 2.DEISUniversity of BolognaBolognaItaly

Personalised recommendations