Boundness Issues in CCSL Specifications

  • Frédéric Mallet
  • Jean-Viven Millo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8144)

Abstract

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on verification techniques supported. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analyses on MARTE models.

This work introduces formally a state-based semantics for CCSL operators and then focuses on the analysis capabilities of MARTE/CCSL and more particularly on boundness issues.

The approach is illustrated on one simple example where the architecture plays an important role. We describe a process where the logical description of the application is progressively refined to take into account the candidate execution platforms through allocation.

Keywords

Logical Time Architecture-driven analysis UML MARTE Reachability analysis 

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References

  1. 1.
    OMG: UML Profile for MARTE, v1.0. Object Management Group. (November 2009) formal/2009-11-02Google Scholar
  2. 2.
    André, C., Mallet, F., de Simone, R.: Modeling time(s). In: Engels, G., Opdyke, B., Schmidt, D.C., Weil, F. (eds.) MODELS 2007. LNCS, vol. 4735, pp. 559–573. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  3. 3.
    André, C.: Syntax and semantics of the Clock Constraint Specification Language (CCSL). Research Report 6925, INRIA (May 2009)Google Scholar
  4. 4.
    DeAntoni, J., Mallet, F.: Timesquare: Treat your models with logical time. In: Furia, C.A., Nanz, S. (eds.) TOOLS 2012. LNCS, vol. 7304, pp. 34–41. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  5. 5.
    Benveniste, A., Caspi, P., Edwards, S.A., Halbwachs, N., Le Guernic, P., de Simone, R.: The synchronous languages 12 years later. Proc. of the IEEE 91(1), 64–83 (2003)CrossRefGoogle Scholar
  6. 6.
    Le Guernic, P., Talpin, J.P., Le Lann, J.C.: Polychrony for system design. Journal of Circuits, Systems, and Computers 12(3), 261–304 (2003)CrossRefGoogle Scholar
  7. 7.
    Lee, E.A., Sangiovanni-Vincentelli, A.L.: A framework for comparing models of computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(12), 1217–1229 (1998)CrossRefGoogle Scholar
  8. 8.
    Arnold, A.: Finite transition systems - semantics of communicating systems. Int. Series in Computer Science. Prentice Hall (1994)Google Scholar
  9. 9.
    Kahn, G.: The semantics of simple language for parallel programming. In: IFIP Congress, pp. 471–475 (1974)Google Scholar
  10. 10.
    Buck, J.T.: Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. PhD thesis, U.C. Berkeley (1993)Google Scholar
  11. 11.
    Commoner, F., Holt, A.W., Even, S., Pnueli, A.: Marked directed graphs. J. Comput. Syst. Sci. 5(5), 511–523 (1971)MathSciNetCrossRefMATHGoogle Scholar
  12. 12.
    Lee, E., Messerschmitt, D.: Synchronous data flow. Proceedings of the IEEE 75(9), 1235–1245 (1987)CrossRefGoogle Scholar
  13. 13.
    Feiler, P.H., Hansson, J.: Flow latency analysis with the architecture analysis and design language. Technical Report CMU/SEI-2007-TN-010, CMU (June 2007)Google Scholar
  14. 14.
    Society of Automotive Engineers, SAE Architecture Analysis and Design Language (AADL) (June 2006) document number: AS5506/1Google Scholar
  15. 15.
    Yin, L., Mallet, F., Liu, J.: Verification of MARTE/CCSL time requirements in Promela/SPIN. In: ICECCS, pp. 65–74. IEEE Computer Society (2011)Google Scholar
  16. 16.
    Gascon, R., Mallet, F., DeAntoni, J.: Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL. In: Combi, C., Leucker, M., Wolter, F. (eds.) TIME, pp. 141–148. IEEE (2011)Google Scholar
  17. 17.
    Romenska, Y., Mallet, F.: Lazy parallel synchronous composition of infinite transition systems. In: ICTERI. CEUR Workshop Proc., vol. 1000, pp. 130–145 (2013)Google Scholar
  18. 18.
    Amnell, T., Fersman, E., Mokrushin, L., Pettersson, P., Yi, W.: Times: A tool for schedulability analysis and code generation of real-time systems. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, pp. 60–72. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  19. 19.
    Krčál, P., Yi, W.: Decidable and undecidable problems in schedulability analysis using timed automata. In: Jensen, K., Podelski, A. (eds.) TACAS 2004. LNCS, vol. 2988, pp. 236–250. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  20. 20.
    Abdeddaim, Y., Asarin, E., Maler, O.: Scheduling with timed automata. Theoretical Computer Science 354(2), 272–300 (2006)MathSciNetCrossRefMATHGoogle Scholar
  21. 21.
    Alur, R., Dill, D.L.: A theory of timed automata. Theor. Comput. Sci. 126(2), 183–235 (1994)MathSciNetCrossRefMATHGoogle Scholar
  22. 22.
    Alur, R., Weiss, G.: Regular specifications of resource requirements for embedded control software. In: IEEE Real-Time and Embedded Technology and Applications Symp., pp. 159–168. IEEE CS (2008)Google Scholar
  23. 23.
    Alur, R., Weiss, G.: Rtcomposer:a framework for real-time components with scheduling interfaces. In: Int. Conf. on Embedded Software, EMSOFT 2008, pp. 159–168. ACM (2008)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Frédéric Mallet
    • 1
  • Jean-Viven Millo
    • 2
  1. 1.I3S, INRIA, CNRSUniv. Nice Sophia AntipolisFrance
  2. 2.I3S, INRIA, CNRSINRIA Sophia Antipolis MéditerranéeFrance

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