Mobile, Ubiquitous, and Intelligent Computing pp 315-320 | Cite as
Microscopic Bit-Level Wear-Leveling for NAND Flash Memory
Abstract
By microscopically observing widely used data files, we identified the considerable room for life time improvement in NAND flash memory, which is due to the discovery of a non-uniformity in bit-level data patterns. In an attempt to exploit the discovery, we propose a novel bit-level wear-leveling scheme. Instead of considering only the view of page-level or block-level, we incorporate the non-uniformity in data encoding patterns into wear-leveling scheme. Because of its orthogonality to the existing block-level wear-leveling approaches, our solution can be adopted over the existing solutions without considerable overhead and extend NAND flash’s life span up to 36% in case of SLC.
Keywords
Data Pattern Page Size NAND Flash Tunnel Oxide Error Correction AlgorithmPreview
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