Advertisement

Accurate Computation of Sensitizable Paths Using Answer Set Programming

  • Benjamin Andres
  • Matthias Sauer
  • Martin Gebser
  • Tobias Schubert
  • Bernd Becker
  • Torsten Schaub
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8148)

Abstract

Precise knowledge of the longest sensitizable paths in a circuit is crucial for various tasks in computer-aided design, including timing analysis, performance optimization, delay testing, and speed binning. As delays in today’s nanoscale technologies are increasingly affected by statistical parameter variations, there is significant interest in obtaining sets of paths that are within a length range. For instance, such path sets can be used in the emerging areas of Post-silicon validation and characterization and Adaptive Test. We present an ASP-based method for computing well-defined sets of sensitizable paths within a length range. Unlike previous approaches, the method is accurate and does not rely on a priori relaxations. Experimental results demonstrate the applicability and scalability of our method.

Keywords

Truth Assignment Gate Delay Benchmark Circuit Input Gate Automatic Test Pattern Generation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    International Technology Roadmap For Semiconductors, http://www.itrs.net
  2. 2.
    Nangate 45nm open cell library, http://www.nangate.com
  3. 3.
    Andres, B., Sauer, M., Gebser, M., Schubert, T., Becker, B., Schaub, T.: Accurate computation of longest sensitizable paths using answer set programming. In: Drechsler, R., Fey, G. (eds.) Sechste GMM/GI/ITG-Fachtagung für Zuverlässigkeit und Entwurf, ZuE 2012 (2012)Google Scholar
  4. 4.
    Baral, C.: Knowledge Representation, Reasoning and Declarative Problem Solving. Cambridge University Press (2003)Google Scholar
  5. 5.
    Biere, A., Heule, M., van Maaren, H., Walsh, T. (eds.): Handbook of Satisfiability. Frontiers in Artificial Intelligence and Applications, vol. 185. IOS Press (2009)Google Scholar
  6. 6.
    Chung, J., Xiong, J., Zolotov, V., Abraham, J.: Testability driven statistical path selection. In: 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC, pp. 417–422 (June 2011)Google Scholar
  7. 7.
    Coudert, O.: An efficient algorithm to verify generalized false paths. In: 2010 47th ACM/IEEE Design Automation Conference, DAC, pp. 188–193 (June 2010)Google Scholar
  8. 8.
    Das, P., Gupta, S.K.: On generating vectors for accurate post-silicon delay characterization. In: 2011 20th Asian Test Symposium, ATS, pp. 251–260 (November 2011)Google Scholar
  9. 9.
    Gebser, M., Kaminski, R., Kaufmann, B., Ostrowski, M., Schaub, T., Thiele, S.: A user’s guide to gringo, clasp, clingo, and iclingo, http://potassco.sourceforge.net
  10. 10.
    Gebser, M., Kaminski, R., Kaufmann, B., Schaub, T.: Answer Set Solving in Practice. Synthesis Lectures on Artificial Intelligence and Machine Learning. Morgan and Claypool Publishers (2012)Google Scholar
  11. 11.
    Jiang, J., Sauer, M., Czutro, A., Becker, B., Polian, I.: On the optimality of k longest path generation algorithm under memory constraints. In: Design, Automation and Test in Europe, DATE (2012)Google Scholar
  12. 12.
    Killpack, K., Kashyap, C., Chiprout, E.: Silicon speedpath measurement and feedback into eda flows. In: 44th ACM/IEEE Design Automation Conference, DAC 2007, pp. 390–395 (June 2007)Google Scholar
  13. 13.
    Kumar, M.M.V., Tragoudas, S.: High-quality transition fault ATPG for small delay defects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(5), 983–989 (2007)CrossRefGoogle Scholar
  14. 14.
    Maxwell, P.: Adaptive test directions. In: 2010 15th IEEE European Test Symposium, ETS, pp. 12–16 (May 2010)Google Scholar
  15. 15.
    Qiu, W., Walker, D.M.H.: An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In: Proceedings of the International Test Conference, ITC 2003, September 30-October 2, vol. 1, pp. 592–601 (2003)Google Scholar
  16. 16.
    Sauer, M., Czutro, A., Schubert, T., Hillebrecht, S., Polian, I., Becker, B.: SAT-based analysis of sensitisable paths. In: 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits Systems, DDECS, pp. 93–98 (April 2011)Google Scholar
  17. 17.
    Sauer, M., Jiang, J., Czutro, A., Polian, I., Becker, B.: Efficient SAT-based search for longest sensitisable paths. In: 2011 20th Asian Test Symposium, ATS, pp. 108–113 (November 2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Benjamin Andres
    • 1
  • Matthias Sauer
    • 2
  • Martin Gebser
    • 1
  • Tobias Schubert
    • 2
  • Bernd Becker
    • 2
  • Torsten Schaub
    • 1
  1. 1.University of PotsdamPotsdamGermany
  2. 2.Albert-Ludwigs-University FreiburgFreiburgGermany

Personalised recommendations