Verifying MARTE/CCSL Mode Behaviors Using UPPAAL

  • Jagadish Suryadevara
  • Cristina Seceleanu
  • Frédéric Mallet
  • Paul Pettersson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8137)


In the development of safety-critical embedded systems, the ability to formally analyze system behavior models, based on timing and causality, helps the designer to get insight into the systems overall timing behavior. To support the design and analysis of real-time embedded systems, the UML modeling profile MARTE provides CCSL – a time model and a clock constraint specification language. CCSL is an expressive language that supports specification of both logical and chronometric constraints for MARTE models. On the other hand, semantic frameworks such as timed automata provide verification support for real-time systems. To address the challenge of verifying CCSL-based behavior models, in this paper, we propose a technique for transforming MARTE/CCSL mode behaviors into Timed Automata for model-checking using the UPPAAL tool. This enables verification of both logical and chronometric properties of the system, which has not been possible before. We demonstrate the proposed transformation and verification approach using two relevant examples of real-time embedded systems.


MARTE CCSL Modes Verification Model-checking UPPAAL 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Jagadish Suryadevara
    • 1
  • Cristina Seceleanu
    • 1
  • Frédéric Mallet
    • 2
  • Paul Pettersson
    • 1
  1. 1.Mälardalen Real-Time Research CentreMälardalen UniversityVästeråsSweden
  2. 2.Aoste Team-project INRIA/I3SSophia-AntipolisFrance

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