Verifying MARTE/CCSL Mode Behaviors Using UPPAAL

  • Jagadish Suryadevara
  • Cristina Seceleanu
  • Frédéric Mallet
  • Paul Pettersson
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8137)

Abstract

In the development of safety-critical embedded systems, the ability to formally analyze system behavior models, based on timing and causality, helps the designer to get insight into the systems overall timing behavior. To support the design and analysis of real-time embedded systems, the UML modeling profile MARTE provides CCSL – a time model and a clock constraint specification language. CCSL is an expressive language that supports specification of both logical and chronometric constraints for MARTE models. On the other hand, semantic frameworks such as timed automata provide verification support for real-time systems. To address the challenge of verifying CCSL-based behavior models, in this paper, we propose a technique for transforming MARTE/CCSL mode behaviors into Timed Automata for model-checking using the UPPAAL tool. This enables verification of both logical and chronometric properties of the system, which has not been possible before. We demonstrate the proposed transformation and verification approach using two relevant examples of real-time embedded systems.

Keywords

MARTE CCSL Modes Verification Model-checking UPPAAL 

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References

  1. 1.
    Alur, R., Dill, D.: A theory of timed automata. Theoretical Computer Science 126(2), 183–235 (1994)MathSciNetCrossRefMATHGoogle Scholar
  2. 2.
    Amnell, T., Fersman, E., Mokrushin, L., Pettersson, P., Yi, W.: TIMES: a Tool for Schedulability Analysis and Code Generation of Real-Time Systems. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, Springer, Heidelberg (2004)CrossRefGoogle Scholar
  3. 3.
    André, C., Mallet, F., de Simone, R.: Modeling Time(s). In: Engels, G., Opdyke, B., Schmidt, D.C., Weil, F. (eds.) MoDELS 2007. LNCS, vol. 4735, pp. 559–573. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  4. 4.
    André, C.: Syntax and Semantics of the Clock Constraint Specification Language (CCSL). Rapport de recherche RR-6925, INRIA (2009)Google Scholar
  5. 5.
    André, C., Mallet, F., DeAntoni, J.: VHDL observers for clock constraint checking. In: 2010 Int. Symp. on Industrial Embedded Systems (SIES), pp. 98–107 (July 2010)Google Scholar
  6. 6.
    Arnold, A.: Finite transition systems - semantics of communicating systems. Int. Series in Computer Science. Prentice Hall (1994)Google Scholar
  7. 7.
    Baier, C., Katoen, J.P.: Principles of Model Checking. Representation and Mind Series. The MIT Press (2008)Google Scholar
  8. 8.
    Bouyssounouse, B., Sifakis, J. (eds.): Embedded Systems Design: The ARTIST Roadmap for Research and Development. LNCS, vol. 3436. Springer, Heidelberg (2005)Google Scholar
  9. 9.
    DeAntoni, J., Mallet, F.: TimeSquare: Treat Your Models with Logical Time. In: Furia, C.A., Nanz, S. (eds.) TOOLS 2012. LNCS, vol. 7304, pp. 34–41. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  10. 10.
    Jahanian, F., Mok, A.: Modechart: a specification language for real-time systems. IEEE Transactions on Software Engineering 20(12), 933–947 (December)Google Scholar
  11. 11.
    Larsen, K.G., Pettersson, P., Yi, W.: Uppaal in a Nutshell. Int. Journal on Software Tools for Technology Transfer 1(1-2), 134–152 (1997)CrossRefMATHGoogle Scholar
  12. 12.
    Mallet, F.: Automatic Generation of Observers from MARTE/CCSL. In: Int. Symp. on Rapid System Prototyping - RSP 2012. IEEE, Tampere (2012), http://hal.inria.fr/hal-00764066 Google Scholar
  13. 13.
    Mallet, F., André, C.: On the semantics of UML/Marte Clock Constraints. In: Int. Symp. on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2009), pp. 301–312. IEEE, Tokyo (2009), http://hal.inria.fr/inria-00383279 Google Scholar
  14. 14.
    OMG: UML Profile for MARTE, v1.0. Object Management Group (November 2009), formal/(2009-11-02)Google Scholar
  15. 15.
    Wang, Z., Pu, G., Li, J., He, J., Qin, S., Larsen, K.G., Madsen, J., Gu, B.: MDM: A Mode Diagram Modeling Framework. In: Proc. First International Workshop on Formal Techniques for Safety-Critical Systems, pp. 135–149. EPTCS (2012)Google Scholar
  16. 16.
    Yin, L., Mallet, F., Liu, J.: Verification of MARTE/CCSL time requirements in Promela/SPIN. In: 2011 16th IEEE Int. Conf. on Engineering of Complex Computer Systems (ICECCS), pp. 65–74 (April 2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Jagadish Suryadevara
    • 1
  • Cristina Seceleanu
    • 1
  • Frédéric Mallet
    • 2
  • Paul Pettersson
    • 1
  1. 1.Mälardalen Real-Time Research CentreMälardalen UniversityVästeråsSweden
  2. 2.Aoste Team-project INRIA/I3SSophia-AntipolisFrance

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