Impact of Resource Sharing on Performance and Performance Prediction: A Survey

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8052)


Multi-core processors are increasingly considered as execution platforms for embedded systems because of their good performance/ energy ratio. However, the interference on shared resources poses several problems. It may severely reduce the performance of tasks executed on the cores, and it increases the complexity of timing analysis and/or decreases the precision of its results. In this paper, we survey recent work on the impact of shared buses, caches, and other resources on performance and performance prediction.


Shared Resource Memory Hierarchy Access Delay Partition Size Cache Space 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Ungerer, T., Cazorla, F., Sainrat, P., Bernat, G., Petrov, Z., Rochange, C., Quinones, E., Gerdes, M., Paolieri, M., Wolf, J., Casse, H., Uhrig, S., Guliashvili, I., Houston, M., Kluge, F., Metzlaff, S., Mische, J.: Merasa: Multicore execution of hard real-time applications supporting analyzability. IEEE Micro 30, 66–75 (2010)CrossRefGoogle Scholar
  2. 2.
    Wilhelm, R., Grund, D., Reineke, J., Schlickling, M., Pister, M., Ferdinand, C.: Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 28(7), 966–978 (2009)CrossRefGoogle Scholar
  3. 3.
    FlexRay Consortium: FlexRay,
  4. 4.
  5. 5.
    Robert Bosch GmbH: FlexRay communication controller IP,
  6. 6.
    Schranzhofer, A., Chen, J.J., Thiele, L.: Timing analysis for TDMA arbitration in resource sharing systems. In: Proceedings of the 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2010, pp. 215–224. IEEE Computer Society, Washington, DC (2010)CrossRefGoogle Scholar
  7. 7.
    Pellizzoni, R., Caccamo, M.: Impact of peripheral-processor interference on WCET analysis of real-time embedded systems. IEEE Transactions on Computers 59, 400–415 (2010)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Pellizzoni, R., Schranzhofer, A., Chen, J.J., Caccamo, M., Thiele, L.: Worst case delay analysis for memory interference in multicore systems. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2010, 3001 Leuven, Belgium, pp. 741–746. European Design and Automation Association (2010)Google Scholar
  9. 9.
    Schranzhofer, A., Pellizzoni, R., Chen, J.J., Thiele, L., Caccamo, M.: Timing analysis for resource access interference on adaptive resource arbiters. In: Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2011, pp. 213–222. IEEE Computer Society, Washington, DC (2011)CrossRefGoogle Scholar
  10. 10.
    Rosen, J., Andrei, A., Eles, P., Peng, Z.: Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In: Proceedings of the 28th IEEE International Real-Time Systems Symposium, RTSS 2007, pp. 49–60. IEEE Computer Society, Washington, DC (2007)Google Scholar
  11. 11.
    Boniol, F., Cassé, H., Noulard, E., Pagetti, C.: Deterministic execution model on COTS hardware. In: Herkersdorf, A., Römer, K., Brinkschulte, U. (eds.) ARCS 2012. LNCS, vol. 7179, pp. 98–110. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  12. 12.
    Cruz, R.L.: A calculus for network delay. IEEE Transactions on Information Theory 37(1), 114–141 (1991)MathSciNetzbMATHCrossRefGoogle Scholar
  13. 13.
    Wandeler, E., Thiele, L., Verhoef, M., Lieverse, P.: System architecture evaluation using modular performance analysis: a case study. Int. J. Softw. Tools Technol. Transf. 8(6), 649–667 (2006)CrossRefGoogle Scholar
  14. 14.
    Reineke, J., Grund, D., Berg, C., Wilhelm, R.: Timing predictability of cache replacement policies. Real-Time Systems 37(2), 99–122 (2007)zbMATHCrossRefGoogle Scholar
  15. 15.
    Zhang, X., Dwarkadas, S., Shen, K.: Towards practical page coloring-based multicore cache management. In: Proceedings of the 4th ACM European conference on Computer systems, EuroSys 2009, pp. 89–102. ACM, New York (2009)Google Scholar
  16. 16.
    Suhendra, V., Mitra, T.: Exploring locking & partitioning for predictable shared caches on multi-cores. In: Proceedings of the 45th Annual Design Automation Conference, DAC 2008, pp. 300–303. ACM, New York (2008)CrossRefGoogle Scholar
  17. 17.
    Nesbit, K.J., Laudon, J., Smith, J.E.: Virtual private caches. SIGARCH Comput. Archit. News 35(2), 57–68 (2007)CrossRefGoogle Scholar
  18. 18.
    Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In: IEEE/ACM International Symposium on Microarchitecture, MICRO 2006, pp. 423–432. IEEE Computer Society (2006)Google Scholar
  19. 19.
    Xie, Y., Loh, G.H.: PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA 2009, pp. 174–183. ACM, New York (2009)CrossRefGoogle Scholar
  20. 20.
    Taylor, G., Davies, P., Farmwald, M.: The TLB slice – a low-cost high-speed address translation mechanism. SIGARCH Comput. Archit. News 18(3a), 355–363 (1990)CrossRefGoogle Scholar
  21. 21.
    Tam, D., Azimi, R., Soares, L., Stumm, M.: Managing shared L2 caches on multicore systems in software. In: Workshop on the Interaction between Operating Systems and Computer Architecture (2007)Google Scholar
  22. 22.
    Zhao, L., Iyer, R., Illikkal, R., Moses, J., Makineni, S., Newell, D.: CacheScouts: Fine-grain monitoring of shared caches in CMP platforms. In: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007, pp. 339–352. IEEE Computer Society, Washington, DC (2007)Google Scholar
  23. 23.
    Guan, N., Stigge, M., Yi, W., Yu, G.: Cache-aware scheduling and analysis for multicores. In: Proceedings of the Seventh ACM International Conference on Embedded Software, EMSOFT 2009, pp. 245–254. ACM, New York (2009)CrossRefGoogle Scholar
  24. 24.
    Akesson, B., Goossens, K., Ringhofer, M.: Predator: a predictable SDRAM memory controller. In: CODES+ISSS, pp. 251–256. ACM (2007)Google Scholar
  25. 25.
    Paolieri, M., Quiñones, E., Cazorla, F., Valero, M.: An analyzable memory controller for hard real-time CMPs. IEEE Embedded Systems Letters 1(4), 86–90 (2010)CrossRefGoogle Scholar
  26. 26.
    Reineke, J., Liu, I., Patel, H.D., Kim, S., Lee, E.A.: PRET DRAM controller: bank privatization for predictability and temporal isolation. In: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, pp. 99–108. ACM, New York (2011)CrossRefGoogle Scholar
  27. 27.
    Radojković, P., Girbal, S., Grasset, A., Quiñones, E., Yehia, S., Cazorla, F.J.: On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM Trans. Archit. Code Optim. (2012)Google Scholar
  28. 28.
    Nowotsch, J., Paulitsch, M.: Leveraging multi-core computing architectures in avionics. In: EDCC (2012)Google Scholar
  29. 29.
    Fernandez, M., Gioiosa, R., Quiñones, E., Fossati, L., Zulianello, M., Cazorla, F.J.: Assessing the suitability of the NGMP multi-core processor in the space domain. In: EMSOFT (2012)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Saarland UniversitySaarbrückenGermany

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