Formal Verification of Hardware Synthesis

  • Thomas Braibant
  • Adam Chlipala
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8044)


We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.


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© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Thomas Braibant
    • 1
  • Adam Chlipala
    • 2
  1. 1.Inria Paris-RocquencourtFrance

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