Formal Verification of Hardware Synthesis

  • Thomas Braibant
  • Adam Chlipala
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8044)


We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.


Hardware Design Atomic Action Memory Element Transactional Memory Hardware Description Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Augustsson, L., Schwarz, J., Nikhil, R.S.: Bluespec Language definition (2001)Google Scholar
  2. 2.
    Benton, N., Hur, C.-K., Kennedy, A., McBride, C.: Strongly Typed Term Representations in Coq. J. Autom. Reasoning 49(2), 141–159 (2012)MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Berry, G.: The foundations of Esterel. In: Proof, Language, and Interaction, Essays in Honour of Robin Milner. MIT Press (2000)Google Scholar
  4. 4.
    Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D., Paul, W.J.: Putting it all together - Formal verification of the VAMP. STTT 8(4-5), 411–430 (2006)CrossRefGoogle Scholar
  5. 5.
    Bjesse, P., Claessen, K., Sheeran, M., Singh, S.: Lava: Hardware Design in Haskell. In: Proc. ICFP, pp. 174–184. ACM Press (1998)Google Scholar
  6. 6.
    Bove, A., Coquand, T.: Formalising bitonic sort in type theory. In: Filliâtre, J.-C., Paulin-Mohring, C., Werner, B. (eds.) TYPES 2004. LNCS, vol. 3839, pp. 82–97. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  7. 7.
    Chlipala, A.: Parametric higher-order abstract syntax for mechanized semantics. In: Proc. ICFP, pp. 143–156. ACM (2008)Google Scholar
  8. 8.
    Chlipala, A.: A verified compiler for an impure functional language. In: Proc. POPL, pp. 93–106. ACM (2010)Google Scholar
  9. 9.
    Claessen, K., Sheeran, M., Singh, S.: The design and verification of a sorter core. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 355–369. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  10. 10.
    Cormen, T.H., Leiserson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms, 2nd edn. The MIT Press and McGraw-Hill Book Company (2001)Google Scholar
  11. 11.
    Coupet-Grimal, S., Jakubiec, L.: Certifying circuits in type theory. Formal Asp. Comput. 16(4), 352–373 (2004)CrossRefzbMATHGoogle Scholar
  12. 12.
    Dave, N., Arvind, Pellauer, M.: Scheduling as rule composition. In: Proc. MEMOCODE, pp. 51–60. IEEE (2007)Google Scholar
  13. 13.
  14. 14.
    Gordon, M.: Why Higher-Order Logic is a Good Formalism for Specifying and Verifying Hardware (1985)Google Scholar
  15. 15.
    Gordon, M.J.C.: Relating Event and Trace Semantics of Hardware Description Languages. Comput. J. 45(1), 27–36 (2002)CrossRefGoogle Scholar
  16. 16.
    Hanna, F.K., Daeche, N., Longley, M.: Veritas + : A Specification Language Based on Type Theory. In: Leeser, M., Brown, G. (eds.) Hardware Specification, Verification and Synthesis: Mathematical Aspects. LNCS, vol. 408, pp. 358–379. Springer, Heidelberg (1990)CrossRefGoogle Scholar
  17. 17.
  18. 18.
    Hunt Jr., W.A., Brock, B.: The Verification of a Bit-slice ALU. In: Leeser, M., Brown, G. (eds.) Hardware Specification, Verification and Synthesis: Mathematical Aspects. LNCS, vol. 408, pp. 282–306. Springer, Heidelberg (1990)CrossRefGoogle Scholar
  19. 19.
    Leroy, X.: A formally verified compiler back-end. Journal of Automated Reasoning 43(4), 363–446 (2009)MathSciNetCrossRefzbMATHGoogle Scholar
  20. 20.
    Nikhil, R.S., Czeck, K.R.: BSV by Example (2010)Google Scholar
  21. 21.
    Pfenning, F., Elliott, C.: Higher-Order Abstract Syntax. In: Proc. PLDI, pp. 199–208. ACM (1988)Google Scholar
  22. 22.
    Richards, D., Lester, D.R.: A monadic approach to automated reasoning for Bluespec SystemVerilog. ISSE 7(2), 85–95 (2011)Google Scholar
  23. 23.
    Schneider, K.: Embedding Imperative Synchronous Languages in Interactive Theorem Provers. In: Proc. ACSD, pp. 143–154. IEEE Computer Society (2001)Google Scholar
  24. 24.
    Schneider, K.: The Synchronous Programming Language Quartz. Technical report, University of Kaiserslautern (2010)Google Scholar
  25. 25.
    Sheeran, M.: Hardware Design and Functional Programming: a Perfect Match. J. UCS 11(7), 1135–1158 (2005)Google Scholar
  26. 26.
    Slind, K., Owens, S., Iyoda, J., Gordon, M.: Proof producing synthesis of arithmetic and cryptographic hardware. Formal Asp. Comput. 19(3), 343–362 (2007)CrossRefzbMATHGoogle Scholar
  27. 27.
    Slobodová, A., Davis, J., Swords, S., Hunt Jr., W.A.: A flexible formal verification framework for industrial scale validation. In: Proc. MEMOCODE, pp. 89–97. IEEE (2011)Google Scholar
  28. 28.
    IEEE Standard System C Language Reference Manual (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Thomas Braibant
    • 1
  • Adam Chlipala
    • 2
  1. 1.Inria Paris-RocquencourtFrance

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