From Arrows to Netlists Describing Hardware

  • Matthias Brettschneider
  • Tobias Häberlein
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7973)

Abstract

This paper describes how to transform a functional domain specific langauge (DSL) into hardware represented by a netlist. In earlier papers we proposed the usage of an algebraic structure called “arrows” (basically an abstraction of Haskell’s higher-order type (→) for describing DSLs. This structure forms the basis of a novel concept that gives the developer a tool at hand to describe hardware functionally in a natural way. Aside of that an arrow provides not only a tool to synthesize, but to verify and reason about the input DSL. We have taken this concept to the next stage, from a static size length arrow into a fixed size length vector arrows fitting much better to logic gates with a fixed number of in- and output pins. There are many sound possibilities to use the algebraic arrow data structure to model hardware. This paper presents some of them which showed to be most useful. A simple example, the implementation of a cyclic redundancy check (CRC) algorithm, is used to illustrate the presented techniques.

Keywords

Logic Gate Type Family Hardware Component Horn Clause Functional Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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References

  1. 1.
    Bjesse, P., Claessen, K., Sheeran, M., Singh, S.: Lava: Hardware design in haskell. ACM Press (1998)Google Scholar
  2. 2.
    Galois, Inc., Portland, Oregon. Cryptol Programming Guide (October 2008), http://www.galois.com/files/Cryptol/Cryptol_Programming_Guide.pdf
  3. 3.
    Galois, Inc., Portland, Oregon. From Cryptol to FPGA (October 2008), http://www.galois.com/files/Cryptol/Cryptol_Tutorial.pdf
  4. 4.
    Grundy, J., Melham, T., O’Leary, J.: A reflective functional language for hardware design and theorem proving. Journal on Functional Programming 16(2), 157–196 (2006)MathSciNetMATHCrossRefGoogle Scholar
  5. 5.
    Hughes, J.: Generalising monads to arrows. Science of Computer Programming 37, 67–111 (1998)CrossRefGoogle Scholar
  6. 6.
    Kiselyov, O., Lmmel, R., Schupke, K.: Strongly typed heterogeneous collections. In: Proceedings of the Haskell Workshop, Snowbird, Utah (2004)Google Scholar
  7. 7.
    Li, Y., Lesser, M.: HML, a novel hardware description language and its translation to VHDL. IEEE Transactions on VLSI 8(1), 1–8 (2000)CrossRefGoogle Scholar
  8. 8.
    Makinwa, K.: Smart sensors - no signal to small. In: DCIS (2011)Google Scholar
  9. 9.
    Martin-Lf, P.: Intuitionistic type theory. Bibliopolis, Napoli (1984)Google Scholar
  10. 10.
    Mycroft, A., Sharp, R.: The FLaSH compiler: Efficient ciruits from functional specifications. Technical report, University of Cambridge, Computing Laboratory (2000)Google Scholar
  11. 11.
    Mycroft, A., Sharp, R.: Hardware/Software co-design using functional languages. In: Margaria, T., Yi, W. (eds.) TACAS 2001. LNCS, vol. 2031, pp. 236–251. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  12. 12.
    Norell, U.: Towards a practical programming language based on dependent type theory (2007)Google Scholar
  13. 13.
    O’Donnell, J.: Hardware description with recursion equations. In: Proceedings of the IFIP 8th International Symposium on Computer Hardware Description Languages and their Applications, pp. 363–382. North-Holland (April 1987)Google Scholar
  14. 14.
    O’Donnell, J.T.: The Hydra Computer Hardware Description Language. University of Glasgow (2003)Google Scholar
  15. 15.
    Paterson, R.: A new notation for arrows. In: ICFP, pp. 229–240 (2001)Google Scholar
  16. 16.
    Peterson, W.W.: Cyclic codes for error detection. In: Proceedings of the Institute of Radio Engineers, Gainesville, Florida (1961)Google Scholar
  17. 17.
    Sander, I.: System Modeling and Design Refinement in ForSyDe. PhD thesis, Royal Institute of Technology, Stockholm, Sweden (April 2003)Google Scholar
  18. 18.
    Sander, I., Jantsch, A.: System Modeling and Transformational Design Refinement in ForSyDe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(1), 17–32 (2004)CrossRefGoogle Scholar
  19. 19.
    Sharp, R. (ed.): Higher-Level Hardware Synthesis. LNCS, vol. 2963. Springer, Heidelberg (2004)MATHGoogle Scholar
  20. 20.
    Sheeran, M.: μFP: A language for VLSI design. In: LISP and Functional Programming, pp. 104–112 (1984)Google Scholar
  21. 21.
    Yorgey, B.A., Weirich, S., Cretin, J., Jones, S.P., Vytiniotis, D., Magalhães, J.P.: Giving haskell a promotion. In: Proceedings of the 8th ACM SIGPLAN Workshop on Types in Language Design and Implementation, TLDI 2012, pp. 53–66. ACM, New York (2012)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Matthias Brettschneider
    • 1
  • Tobias Häberlein
    • 1
  1. 1.University of Applied Science Albstadt-SigmaringenGermany

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