Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation

  • Charlie Shucheng Zhu
  • Georg Weissenbacher
  • Sharad Malik
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7857)


Post-silicon validation is the time-consuming process of detecting and diagnosing defects in prototype silicon. It targets electrical and functional defects that escaped detection during pre-silicon verification. While the at-speed execution of test scenarios facilitates a higher test coverage than pre-silicon simulation, this comes at the cost of limited observability of signals in the integrated circuit. This limitation complicates the localisation of the cause underlying a defect. Trace buffers, designed to store a limited execution history, partially alleviate but do not entirely remedy the problem. Since trace buffers typically record only a small fraction of the system state over at most a few thousand cycles, their utility is contingent on the cautious selection of traced signals.

This paper presents a technique for the automated selection of trace signals. While the aim of existing selection strategies is typically to enable the (early) detection of defects or to maximise the recoverable state information, our objective is to facilitate the subsequent automated localisation of faults using consistency-based diagnosis. To this end, we use integer linear programming and automated test pattern generation to identify a subset of state signals through which potential failures are likely to propagate. We demonstrate that our technique complements our previous work on SAT-based fault localisation using backbones. In that context, we evaluate the utility of our results on two OpenCores designs. We show that for this purpose, our technique generates a better selection of trace signals than a related approach recently presented by Yang and Touba.


Integer Linear Programming Fault Localisation Fault Simulation Transmission Matrix Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital systems testing and testable design. Computer Science Press (1990)Google Scholar
  2. 2.
    Brillout, A., He, N., Mazzucchi, M., Kroening, D., Purandare, M., Rümmer, P., Weissenbacher, G.: Mutation-based test case generation for simulink models. In: de Boer, F.S., Bonsangue, M.M., Hallerstede, S., Leuschel, M. (eds.) FMCO 2009. LNCS, vol. 6286, pp. 208–227. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  3. 3.
    Chen, Y., Safarpour, S., Marques-Silva, J., Veneris, A.: Automated design debugging with maximum satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 29, 1804–1817 (2010)CrossRefGoogle Scholar
  4. 4.
    Chen, Y., Safarpour, S., Veneris, A., Marques-Silva, J.: Spatial and temporal design debug using partial MaxSAT. In: Great Lakes Symposium on VLSI, pp. 345–350. ACM (2009)Google Scholar
  5. 5.
    Cheng, K.-T., Wang, L.-C.: Automatic test pattern generation. In: EDA for IC System Design, Verification, and Testing. CRC Press (2006)Google Scholar
  6. 6.
    Craig, W.: Linear reasoning. A new form of the Herbrand-Gentzen theorem 22(3), 250–268 (1957)MathSciNetzbMATHGoogle Scholar
  7. 7.
    De Paula, F.M., Gort, M., Hu, A.J., Wilton, S.J.E., Yang, J.: Backspace: formal analysis for post-silicon debug. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 5:1–5:10. IEEE (2008)Google Scholar
  8. 8.
    de Paula, F.M., Nahir, A., Nevo, Z., Orni, A., Hu, A.J.: TAB-Backspace: unlimited-length trace buffers with zero additional on-chip overhead. In: Proceedings of the 48th Design Automation Conference (DAC), pp. 411–416. ACM (2011)Google Scholar
  9. 9.
    Eén, N., Sörensson, N.: An extensible SAT-solver. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 502–518. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  10. 10.
    Fu, Z., Malik, S.: On solving the partial MAX-SAT problem. In: Biere, A., Gomes, C.P. (eds.) SAT 2006. LNCS, vol. 4121, pp. 252–265. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  11. 11.
    Hung, E., Wilton, S.: On evaluating signal selection algorithms for post-silicon debug. In: Quality Electronic Design, ISQED (March 2011)Google Scholar
  12. 12.
    Keng, B., Safarpour, S., Veneris, A.G.: Bounded model debugging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 29(11), 1790–1803 (2010)CrossRefGoogle Scholar
  13. 13.
    Marques-Silva, J., Janota, M., Lynce, I.: On computing backbones of propositional theories. In: European Conference on Artificial Intelligence (ECAI), pp. 15–20. IOS Press (2010)Google Scholar
  14. 14.
    Moskewicz, M.W., Madigan, C.F., Zhao, Y., Zhang, L., Malik, S.: Chaff: engineering an efficient SAT solver. In: Design Automation Conference (DAC), pp. 530–535. ACM (2001)Google Scholar
  15. 15.
    Prabhakar, S., Hsiao, M.: Multiplexed trace signal selection using non-trivial implication-based correlation. In: Quality Electronic Design (ISQED), pp. 697–704 (2010)Google Scholar
  16. 16.
    Reiter, R.: A theory of diagnosis from first principles. Artificial Intelligence 32(1), 57–95 (1987)MathSciNetzbMATHCrossRefGoogle Scholar
  17. 17.
    Safarpour, S., Mangassarian, H., Veneris, A.G., Liffiton, M.H., Sakallah, K.A.: Improved design debugging using maximum satisfiability. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 13–19. IEEE (2007)Google Scholar
  18. 18.
    Sülflow, A., Fey, G., Bloem, R., Drechsler, R.: Using unsatisfiable cores to debug multiple design errors. In: Great Lakes Symposium on VLSI, pp. 77–82. ACM (2008)Google Scholar
  19. 19.
    Yang, J.-S., Touba, N.A.: Efficient trace signal selection for silicon debug by error transmission analysis. IEEE Transactions on CAD of Integrated Circuits and Systems 31(3), 442–446 (2012)CrossRefGoogle Scholar
  20. 20.
    Yang, Y.-S., Keng, B., Nicolici, N., Veneris, A.G., Safarpour, S.: Automated silicon debug data analysis techniques for a hardware data acquisition environment. In: International Symposium on Quality of Electronic Design. IEEE (2010)Google Scholar
  21. 21.
    Zhu, C.S., Weissenbacher, G., Malik, S.: Post-silicon fault localisation using maximum satisfiability and backbones. In: Formal Methods in Computer-Aided Design (FMCAD). IEEE (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Charlie Shucheng Zhu
    • 1
  • Georg Weissenbacher
    • 2
  • Sharad Malik
    • 1
  1. 1.Princeton UniversityUSA
  2. 2.Vienna University of TechnologyAustria

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