Analysis Support for TADL2 Timing Constraints on EAST-ADL Models

  • Arda Goknil
  • Jagadish Suryadevara
  • Marie-Agnès Peraldi-Frati
  • Frédéric Mallet
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7957)

Abstract

It is critical to analyze characteristics of real-time embedded systems, such as timing behavior, early in the development. In the automotive domain, EAST-ADL is a concrete example of the model-based approach for the architectural modeling of real-time systems. The Timing Augmented Description Language v2 (TADL2) allows for the specification of timing constraints on top of EAST-ADL models. In this paper we propose a formal validation & verification methodology for timing behaviors given with TADL2. The formal semantics of the timing constraints is given as a mapping to the Clock Constraint Specification Language (CCSL), a formal language that implements the MARTE Time Model. Based on such a mapping, the validation is carried out by the simulation of TADL2 specifications. The simulation allows for a rapid prototyping of TADL2 specifications. The verification is performed based on a TADL2 mapping to timed automata modeling using the Uppaal model-checker. The whole process is illustrated on a Brake-By-Wire application.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Arda Goknil
    • 1
  • Jagadish Suryadevara
    • 2
  • Marie-Agnès Peraldi-Frati
    • 1
  • Frédéric Mallet
    • 1
  1. 1.AOSTE Team, UNS-I3S-INRIASophia-AntipolisFrance
  2. 2.Formal Modeling and Analysis GroupMälardalen UniversityVästeråsSweden

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