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Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

  • Maher Fakih
  • Kim Grüttner
  • Martin Fränzle
  • Achim Rettberg
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 403)

Abstract

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable when analyzing systems with large number of tasks and processing units. In this paper, a model-checking based approach that allows to guarantee timing bounds of multiple Synchronous Data Flow Applications (SDFA) running on shared-bus multicore architectures will be extended for a TDMA hypervisor architecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.

Keywords

Time Slot Shared Memory First Come First Serve WCET Analysis Transaction Level Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© IFIP International Federation for Information Processing 2013

Authors and Affiliations

  • Maher Fakih
    • 1
  • Kim Grüttner
    • 1
  • Martin Fränzle
    • 2
  • Achim Rettberg
    • 2
  1. 1.OFFIS - Institute for Information TechnologyGermany
  2. 2.Carl von Ossietzky UniversitätGermany

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