Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

  • Maher Fakih
  • Kim Grüttner
  • Martin Fränzle
  • Achim Rettberg
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 403)


The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable when analyzing systems with large number of tasks and processing units. In this paper, a model-checking based approach that allows to guarantee timing bounds of multiple Synchronous Data Flow Applications (SDFA) running on shared-bus multicore architectures will be extended for a TDMA hypervisor architecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.


Time Slot Shared Memory First Come First Serve WCET Analysis Transaction Level Model 
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  1. 1.
    Aeronautical Radio, I.: Arinc 653: Avionics application software standard interface. Technical report, ARINC, 2551 Riva Road Annapolis, MD 21401, U.S.A (2003)Google Scholar
  2. 2.
    Fakih, M., Grüttner, K., Fränzle, M., Rettberg, A.: Towards performance analysis of SDFGs mapped to shared–bus architectures using model–checking. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2013, Leuven, Belgium, European Design and Automation Association (March 2013)Google Scholar
  3. 3.
    Sriram, S., Bhattacharyya, S.S.: Embedded Multiprocessors: Scheduling and Synchronization, 1 edn. CRC Press (March 2000)Google Scholar
  4. 4.
    Lv, M., Yi, W., Guan, N., Yu, G.: Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software. In: 2010 31st IEEE Real-Time Systems Symposium, pp. 339–349 (2010)Google Scholar
  5. 5.
    Gustavsson, A., Ermedahl, A., Lisper, B., Pettersson, P.: Towards WCET Analysis of Multicore Architectures Using UPPAAL. In: 10th, pp. 101–112 (2011)Google Scholar
  6. 6.
    Giannopoulou, G., Lampka, K., Stoimenov, N., Thiele, L.: Timed model checking with abstractions: Towards worst-case response time analysis in resource-sharing manycore systems. In: Proc. International Conference on Embedded Software (EMSOFT), Tampere, Finland, pp. 63–72. ACM (October 2012)Google Scholar
  7. 7.
    Dong-il, C., Hyung, C., Jan, M.: System-Level Verification of Multi-Core Embedded Systems Using Timed-Automata, pp. 9302–9307 (July 2008)Google Scholar
  8. 8.
    Ghamarian, A.: Timing Analysis of Synchronous Data Flow Graphs. PhD thesis, Eindhoven University of Technology (2008)Google Scholar
  9. 9.
    Moonen, A.: Predictable Embedded Multiprocessor Architecture for Streaming Applications. PhD thesis, Eindhoven University of Technology (2009)Google Scholar
  10. 10.
    Kumar, A.: Analysis, Design and Management of Multimedia Multiprocessor Systems. PhD thesis, Ph. D. thesis, Eindhoven University of Technology (2009)Google Scholar
  11. 11.
    Yang, Y., Geilen, M., Basten, T., Stuijk, S., Corporaal, H.: Automated bottleneck-driven design-space exploration of media processing systems. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2010, Leuven, Belgium, pp. 1041–1046. European Design and Automation Association (2010)Google Scholar
  12. 12.
    Shabbir, A., Kumar, A., Stuijk, S., Mesman, B., Corporaal, H.: CA-MPSoC: An Automated Design Flow for Predictable Multi-processor Architectures for Multiple Applications. Journal of Systems Architecture 56(7), 265–277 (2010)CrossRefGoogle Scholar
  13. 13.
    Kumar, A., Mesman, B., Theelen, B., Corporaal, H., Ha, Y.: Analyzing composability of applications on MPSoC platforms. J. Syst. Archit. 54(3-4) (March 2008)Google Scholar
  14. 14.
    Gerstlauer, A., Haubelt, C., Pimentel, A., Stefanov, T., Gajski, D., Teich, J.: Electronic System-Level Synthesis Methodologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28(10), 1517–1530 (2009)CrossRefGoogle Scholar
  15. 15.
    Stuijk, S.: Predictable Mapping of Streaming Applications on Multiprocessors, vol. 68. University Microfilms International, P. O. Box 1764, Ann Arbor, MI, 48106, USA (2007)Google Scholar
  16. 16.
    Cai, L., Gajski, D.: Transaction Level Modeling: an Overview. In: First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 19–24 (October 2003)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2013

Authors and Affiliations

  • Maher Fakih
    • 1
  • Kim Grüttner
    • 1
  • Martin Fränzle
    • 2
  • Achim Rettberg
    • 2
  1. 1.OFFIS - Institute for Information TechnologyGermany
  2. 2.Carl von Ossietzky UniversitätGermany

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